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Otherwise, if the net has enough fanout, Yosys wil...
# openlane
m
Otherwise, if the net has enough fanout, Yosys will add a buffer tree and then CTS will think it only has 1 fanout and not do CTS
m
In openroad-flow-scripts we remove all yosys buffering after synthesis is done and let cts & resizer redo it.
m
Yeah, I just isolated that it is done in step 8, resizer
Even if I disable PL_RESIZER_DESIGN_OPTIMIZATIONS it buffers it
m
it is the clock root coming from a pad?
m
No
It's coming from a mux
m
is it marked as a clock in sta?
m
Yes, it is
I had to do some tricks to get this to work. I made a module with the mux, so that I could set the output port as the clock
Although later, it may flatten that and have the name "\clkmux.clk" whereas clkmux.clk was a hierarchical name
I'm not sure if the escape is causing an issue
m
normally resizer skips clock nets so I'm not sure
the name doesn't matter just whether sta sees it as a clock based on sdc and clock propagation
m
Ok, so that is probably the issue. It's a good direction, thanks.
Yeah, after synthesis it finds the clock fine, but before resizer it doesn't: create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) [WARNING STA-0337] port 'clkmux.clk' not found.
m
that's the problem then
m
But it definitely exists in the def: - clkmux.clk ( 4762 CLK ) ( 4761 CLK ) ...
Ah, this is again because it is looking specifically for a PORT, not a NET and it seems that it flattened my mux module
I'm still stuck how to get the driver of a net in TCL
m
Here's a hint: set block [ord::get_db_block] set net [$block findNet net51] foreach iterm [$net getITerms] { set mterm [$iterm getMTerm] set type [$mterm getIoType] if {$type == "OUTPUT"} { puts "[[$iterm getInst] getName]/[$mterm getName]" } }
you would have to deal with top level terms too if that is relevant
m
I found that I could also use TCL only using get_property. The problem was figuring out what the properties were. I did it by guess and check... pin_direction, direction (yes)
Roughly get_pins, foreach pin get property, return output
m
you can look at db.h as a guide to what's callable
from sta you can do get_pins -of_objects [get_net net51] and write up something similar if that is easier. At least it has a manual (and is basically sdc)
get_property [get_pins -of_objects [get_net net51] -filter direction==output] full_name
seems to work
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