open-source-silicon.dev

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A few digital projects in the Stanford EE 272B course are having issues with met5 stripes being redrawn in the openlane `make user_project_wrapper` flow which causes DRVs in precheck.

We use innovus to harden our design macro which uses met5 as a layer. See 1st screenshot below which shows met5. so far so good.
When then placing that macro in `user_project_wrapper`, the met5 stripes are redrawn - see 2nd screenshot.

How can we prevent openlane from redrawing the stripes and instead connect our design's preexisting power network to the wrapper's rings?

we've tried adding a met5 blockage to the macro in a custom `pdn.tcl` but we then run into the issue that the macro power stripes are not connected to the outer wrapper ring

have you tried with `GLB_RT_OBS` setting?

<@U01L8BR7FFA> that could work for the met5  re-drawing issue but we're also seeing issues with our power network not being connected to the outer rings, but this might be due to the global `met5` blockage we added to the macro.

Have you used this before for macros that have a `met5` layer?

Probably yes, we don’t use `met5` in our macros, but has `met4`and only horizontal `met5` can get through