Mitch Bailey
08/02/2021, 11:33 AMHadir Khan
08/02/2021, 11:37 AMconfig.tcl
# User config
set ::env(DESIGN_NAME) m21
# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_SIZING) "relative"
set ::env(FP_CORE_UTIL) "10"
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
Matt Venn
08/02/2021, 12:49 PMHadir Khan
08/02/2021, 12:50 PMMatt Venn
08/02/2021, 12:51 PMHadir Khan
08/02/2021, 12:52 PMmodule m21(Y, D0, D1, S);
output Y;
input D0, D1, S;
wire T1, T2, Sbar;
and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);
endmodule
Matt Venn
08/02/2021, 12:58 PMHadir Khan
08/02/2021, 1:15 PMconfig.tcl
the flow completed successfully. Strange though!