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#openlane
Title
# openlane
m

Mitch Bailey

08/02/2021, 11:33 AM
@User's top level net doesn't have the VPWR connection defined or routed. Does anyone know what he needs to change in his config file?
h

Hadir Khan

08/02/2021, 11:37 AM
For reference, here is my
config.tcl
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# User config
set ::env(DESIGN_NAME) m21

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""

set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_SIZING) "relative"
set ::env(FP_CORE_UTIL) "10"
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}
m

Matt Venn

08/02/2021, 12:49 PM
do the example designs work?
h

Hadir Khan

08/02/2021, 12:50 PM
Yes the spm and inverter works
m

Matt Venn

08/02/2021, 12:51 PM
have you posted your design files anywhere? would be useful to have everything in one place (design, config)
h

Hadir Khan

08/02/2021, 12:52 PM
Here is the single design file:
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module m21(Y, D0, D1, S);

output Y;
input D0, D1, S;
wire T1, T2, Sbar;

and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);

endmodule
m

Matt Venn

08/02/2021, 12:58 PM
I tried with the inverter config and that finished with no errors
so I would guess it either has something to do with FP_PDN_CHECK_NODES, which I've never used before. Or the die size. I've found with very small designs it's best to set the die size manually as in the inverter example.
h

Hadir Khan

08/02/2021, 1:15 PM
By default FP_PDN_CHECK_NODES=1 which was failing in the floorplanning step. By setting it to 0 the flow progressed however it failed in the LVS check
Thanks @Matt Venn after setting the absolute position and target density from the inverter
config.tcl
the flow completed successfully. Strange though!
🙌 1