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<@U01AW5TSG9J>'s top level net doesn't have the VPWR connection defined or routed. Does anyone know what he needs to change in his config file?

For reference, here is my `config.tcl`
```# User config
set ::env(DESIGN_NAME) m21

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# turn off clock
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(CLOCK_PORT) ""

set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_SIZING) "relative"
set ::env(FP_CORE_UTIL) "10"
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
} ```

have you posted your design files anywhere? would be useful to have everything in one place (design, config)

Here is the single design file:
```module m21(Y, D0, D1, S);

output Y;
input D0, D1, S;
wire T1, T2, Sbar;

and (T1, D1, S), (T2, D0, Sbar);
not (Sbar, S);
or (Y, T1, T2);

endmodule```

I tried with the inverter config and that finished with no errors

so I would guess it either has something to do with FP_PDN_CHECK_NODES, which I've never used before. Or the die size. I've found with very small designs it's best to set the die size manually as in the inverter example.

By default FP_PDN_CHECK_NODES=1 which was failing in the floorplanning step. By setting it to 0 the flow progressed however it failed in the LVS check

Thanks <@U0172QZ342D> after setting the absolute position and target density from the inverter `config.tcl` the flow completed successfully. Strange though!