s top level net doesn t have the VPWR connect

Question

< U01AW5TSG9J> s top level net doesn t have the VPWR connection defined or routed Does anyone know what he needs to change in his config file

Hadir Khan · Answer

For reference here is my `config tcl` ``` User config set env DESIGN NAME m21 Change if needed set env VERILOG FILES glob $ env DESIGN DIR src v turn off clock set env CLOCK TREE SYNTH 0 set env CLOCK PORT set env FP PDN CHECK NODES 0 set env FP SIZING relative set env FP CORE UTIL 10 set filename $ env DESIGN DIR $ env PDK $ env STD CELL LIBRARY config tcl if file exists $filename == 1 source $filename ```

Matt Venn · Answer

do the example designs work

Hadir Khan · Answer

Yes the spm and inverter works

Matt Venn · Answer

have you posted your design files anywhere would be useful to have everything in one place design config

Hadir Khan · Answer

Here is the single design file ```module m21 Y D0 D1 S output Y input D0 D1 S wire T1 T2 Sbar and T1 D1 S T2 D0 Sbar not Sbar S or Y T1 T2 endmodule```

Matt Venn · Answer

I tried with the inverter config and that finished with no errors

Matt Venn · Answer

so I would guess it either has something to do with FP PDN CHECK NODES which I ve never used before Or the die size I ve found with very small designs it s best to set the die size manually as in the inverter example

Hadir Khan · Answer

By default FP PDN CHECK NODES=1 which was failing in the floorplanning step By setting it to 0 the flow progressed however it failed in the LVS check

Hadir Khan · Answer

Thanks < Matt Venn> after setting the absolute position and target density from the inverter `config tcl` the flow completed successfully Strange though