Hi all, this is coming from someone who mostly worked on FPGA designs using Vivado. Is there a methodology for performing timing closure using OpenLANE? When I check the timing report generated by the tool (e.g., synthesis/27-opensta_spef.timing.rpt) I have a hard time understanding what the critical path is (attached is one violated path from the report). In contrast, with Vivado, most of the time I can see the registers & wires that lie on the critical path. How can I make sense out of what is written in the timing report? More specifically, how do the sky130* elements on the path relate to the Verilog design?

It seems the challenge would be yosys is using those generic names…

According to this SO answer Yosys apparently already tries its best to retain the original names of the signals. Do you know if there is a way to make Yosys somehow associate the generated (assuming they are) sky130 elements to their most relevant Verilog signals?

When you use -flatten in yosys it destroys the names. When you don't use -flatten you get terrible area. It's an area that OpenRoad is looking into.