Im getting a small number of LVS errors that mostly seem related to an sram macro and power, any ideas for how to resolve these issues?

@User try to move the macro to its default position indicated in macro.cfg on the craavel_user_project

Move the macro to its default position? Im not sure what you mean

Isnt that for placing the example project in the wrapper? I am current just trying to harden the example, my macro.cfg looks like attached, I just place the sram cell?

change 1000 1000 N to the values indicated above

Hey @User netgen logs can take a while to get used to. Looking at your VGND/VPWR connections from you verilog, you can see the sram connections.

(no matching net)                          |Net: VPWR                                  
                                           |  sky130_fd_sc_hd__diode_2/VPB = 358       
                                           |  sky130_fd_sc_hd__diode_2/VPWR = 358      
                                           |  sky130_fd_sc_hd__decap_6/VPB = 1         
...     
                                           |  sky130_fd_sc_hd__dfxtp_4/VPWR = 33       
                                           |  sky130_fd_sc_hd__clkbuf_16/VPB = 3       
                                           |  sky130_fd_sc_hd__clkbuf_16/VPWR = 3      
HERE ->                                    |  sky130_sram_1kbyte_1rw1r_32x256_8/vccd1  
                                           |  sky130_fd_sc_hd__buf_6/VPB = 5           
                                           |  sky130_fd_sc_hd__buf_6/VPWR = 5          
                                           |  sky130_fd_sc_hd__buf_8/VPB = 12          
                                           |  sky130_fd_sc_hd__buf_8/VPWR = 12         
                                           |                                           
(no matching net)                          |Net: VGND                                  
                                           |  sky130_fd_sc_hd__diode_2/VGND = 358      
                                           |  sky130_fd_sc_hd__diode_2/VNB = 358       
                                           |  sky130_fd_sc_hd__decap_6/VGND = 1        
...      
                                           |  sky130_fd_sc_hd__mux4_1/VGND = 32        
                                           |  sky130_fd_sc_hd__mux4_1/VNB = 32         
                                          |  sky130_fd_sc_hd__dfxtp_4/VGND = 33       
                                           |  sky130_fd_sc_hd__dfxtp_4/VNB = 33        
                                           |  sky130_fd_sc_hd__clkbuf_16/VGND = 3      
                                           |  sky130_fd_sc_hd__clkbuf_16/VNB = 3       
HERE->                                     |  sky130_sram_1kbyte_1rw1r_32x256_8/vssd1  
                                           |  sky130_fd_sc_hd__buf_6/VGND = 5          
                                           |  sky130_fd_sc_hd__buf_6/VNB = 5           
                                           |  sky130_fd_sc_hd__buf_8/VGND = 12         
                                           |  sky130_fd_sc_hd__buf_8/VNB = 12

But the layout is missing sram connections.

Net: VPWR                                  |(no matching net)                          
  sky130_fd_sc_hd__decap_12/VPB = 1        |                                           
...                                      
  sky130_fd_sc_hd__nand2_2/VPB = 1         |                                           
  sky130_fd_sc_hd__nand2_2/VPWR = 1        |                                           
  sky130_fd_sc_hd__o21ba_1/VPB = 1         |                                           
  sky130_fd_sc_hd__o21ba_1/VPWR = 1        |                                           
  sky130_fd_sc_hd__or4_2/VPB = 1           |                                           
  sky130_fd_sc_hd__or4_2/VPWR = 1          |                                           
  sky130_fd_sc_hd__and3_2/VPB = 1          |                                           
  sky130_fd_sc_hd__and3_2/VPWR = 1         |                                           
                                           |                                           
Net: VGND                                  |(no matching net)                          
  sky130_fd_sc_hd__decap_12/VGND = 1       |                                           
  sky130_fd_sc_hd__decap_12/VNB = 1        |                                           
  sky130_fd_sc_hd__tapvpwrvgnd_1/VGND = 1  |                                           
  sky130_fd_sc_hd__fill_1/VGND = 1         |                                           
...                            
  sky130_fd_sc_hd__or4_2/VNB = 1           |                                           
  sky130_fd_sc_hd__and3_2/VGND = 1         |                                           
  sky130_fd_sc_hd__and3_2/VNB = 1          |

Looking at your sram connections, you can see that the vssd1/vccd1 sram layout pins only have 1 connection.

---------------------------------------------------------------------------------------
Instance: sky130_sram_1kbyte_1rw1r_32x256_ |Instance: \i_dpram_gen.genblk2.i_sky130_sr 
  din0[0] = 4                              |  din0[0] = 4                              
  din0[1] = 4                              |  din0[1] = 4                              
  din0[2] = 4                              |  din0[2] = 4                              
...            
  dout1[29] = 1                            |  dout1[29] = 1                            
  dout1[30] = 1                            |  dout1[30] = 1                            
  dout1[31] = 1                            |  dout1[31] = 1                            
  vccd1 = 1                                |  vccd1 = 2532                             
  vssd1 = 1                                |  vssd1 = 2532

I'd check to be sure that your VGND/VPWR connect to the LEF vssd1/vccd1 pins of the sram.

I saw that, but wasnt really sure what it meant, in the bottom readout, the left is the layout and the right is the circuit? Basically I should make sure to connect the power pins in my verilog? Or would there be another reason that the power is unconnected?