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19-opendp.log

Hello all, while running openlane flow, in the detailed placement step, it is failing for all the cells. The flow shows an error that there are lots of overlaps. I tried reducing FP_CORE_UTIL value upto 2, I also tried using absolute FP_SIZING and providing a high DIE_AREA. But still the problem persists.
I have attached the detailed placement log file. I am not sure how to overcome this.

I have change the default 3 to 4 and worked for me

Try to comment this line set ::env(PL_BASIC_PLACEMENT) 1

```
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"
set ::env(CLOCK_PERIOD) "40"

set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2000 2000"

set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(PL_SKIP_INITIAL_PLACEMENT) 0
#set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.35
set ::env(FP_CORE_UTIL) 60
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(DESIGN_IS_CORE) 0

set ::env(ROUTING_CORES) 8


set ::env(BASE_SDC_FILE) "$script_dir/top.sdc"

# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper) 
# where the PDN is planned on metal 5. So, to avoid having shorts between routes
# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
set ::env(GLB_RT_MAXLAYER) 5

# You can draw more power domains if you need to 
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]

set ::env(DIODE_INSERTION_STRATEGY) 4
# If you're going to use multiple power domains, then disable cvc run.
set ::env(RUN_CVC) 1```

24-tritonRoute (1).log

<@U01GLU3UDRD> Now I am getting an error in detailed routing. Will you be able to provide help on this?

The 9119_SETB is a pin generated by the Openlane flow and not from the design

<@U02A70RDME3> I am glad it worked, the other error unfortunately I do not know how to solve it