set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_NET) "wb_clk_i"
set ::env(CLOCK_PERIOD) "40"

set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 2000 2000"

set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(PL_SKIP_INITIAL_PLACEMENT) 0
#set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.35
set ::env(FP_CORE_UTIL) 60
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(DESIGN_IS_CORE) 0

set ::env(ROUTING_CORES) 8


set ::env(BASE_SDC_FILE) "$script_dir/top.sdc"

# Maximum layer used for routing is metal 4.
# This is because this macro will be inserted in a top level (user_project_wrapper) 
# where the PDN is planned on metal 5. So, to avoid having shorts between routes
# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
set ::env(GLB_RT_MAXLAYER) 5

# You can draw more power domains if you need to 
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]

set ::env(DIODE_INSERTION_STRATEGY) 4
# If you're going to use multiple power domains, then disable cvc run.
set ::env(RUN_CVC) 1