[INFO]: Version: 2021.12.01_01.29.55
[INFO]: Running non-interactively
[INFO]: Using design configuration at /openlane/designs/spm/config.tcl
[INFO]: Sourcing Configurations from /openlane/designs/spm/config.tcl
[INFO]: PDKs root directory: /home/shahid/SkywaterPDK/
[INFO]: PDK: sky130A
[INFO]: Setting PDKPATH to /home/shahid/SkywaterPDK//sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library is set to: sky130_fd_sc_hd
[INFO]: Sourcing Configurations from /openlane/designs/spm/config.tcl
[WARNING]: Removing exisiting run /openlane/designs/spm/runs/openlane_test
[INFO]: Current run directory is /openlane/designs/spm/runs/openlane_test
[INFO]: Storing configs into config.tcl ...
[INFO]: Preparing LEF Files
[INFO]: Extracting the number of available metal layers from /home/shahid/SkywaterPDK//sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef
[INFO]: The available metal layers (6) are li1  met1  met2  met3  met4  met5
[INFO]: Merging LEF Files...
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...
[INFO]: Generating Exclude List...
[INFO]: Creating ::env(DONT_USE_CELLS)...
[INFO]: Preparation complete
[INFO]: Incremented step index to 0.
[INFO]: Running Synthesis...
[INFO]: Changing netlist from 0 to /openlane/designs/spm/runs/openlane_test/results/synthesis/spm.v
[INFO]: Incremented step index to 1.
[INFO]: Running Static Timing Analysis...
[INFO]: Synthesis was successful
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
[INFO]: Incremented step index to 2.
[INFO]: Core area width: 87.86
[INFO]: Core area height: 87.04
[WARNING]: Current core area is too small for a power grid
[WARNING]: !!! THE POWER GRID WILL BE MINIMIZED. !!!
[INFO]: Final Vertical PDN Offset: 14.643333333333333
[INFO]: Final Horizontal PDN Offset: 14.506666666666668
[INFO]: Final Vertical PDN Pitch: 29.286666666666665
[INFO]: Final Horizontal PDN Pitch: 29.013333333333335
[INFO]: Changing layout from 0 to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/3-initial_fp.def
[INFO]: Incremented step index to 3.
[INFO]: Running IO Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/3-initial_fp.def to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/4-io.def
[INFO]: Incremented step index to 4.
[INFO]: Running Tap/Decap Insertion...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/4-io.def to /openlane/designs/spm/runs/openlane_test/results/floorplan/spm.def
[INFO]: Power planning the following nets
[INFO]: Power: VPWR
[INFO]: Ground: VGND
[INFO]: Incremented step index to 5.
[INFO]: Generating PDN...
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/floorplan/spm.def to /openlane/designs/spm/runs/openlane_test/tmp/floorplan/6-pdn.def
[INFO]: Running Placement...
[INFO]: Incremented step index to 6.
[INFO]: Running Global Placement...
[INFO]: Global placement was successful
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/floorplan/6-pdn.def to /openlane/designs/spm/runs/openlane_test/tmp/placement/7-global.def
[INFO]: Incremented step index to 7.
[INFO]: Running Resizer Design Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/placement/7-global.def to /openlane/designs/spm/runs/openlane_test/tmp/placement/8-resizer.def
[INFO]: Incremented step index to 8.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/synthesis/spm.v to /openlane/designs/spm/runs/openlane_test/results/placement/spm.resized.v
[INFO]: Incremented step index to 9.
[INFO]: Running Detailed Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/placement/8-resizer.def to /openlane/designs/spm/runs/openlane_test/results/placement/spm.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/placement/spm.def to /openlane/designs/spm/runs/openlane_test/results/placement/spm.def
[INFO]: Incremented step index to 10.
[INFO]: Running TritonCTS...
[INFO]: Trimming Liberty...
[INFO]: Generating Exclude List...
[INFO]: Clock Tree Synthesis was successful
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/placement/spm.def to /openlane/designs/spm/runs/openlane_test/results/cts/spm.def
[INFO]: Incremented step index to 11.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/placement/spm.resized.v to /openlane/designs/spm/runs/openlane_test/results/cts/spm.v
[INFO]: Incremented step index to 12.
[INFO]: Running Resizer Timing Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/results/cts/spm.def to /openlane/designs/spm/runs/openlane_test/tmp/cts/13-resizer_timing.def
[INFO]: Incremented step index to 13.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/cts/spm.v to /openlane/designs/spm/runs/openlane_test/results/cts/spm.resized.v
[INFO]: Routing...
[INFO]: Incremented step index to 14.
[INFO]: Running Resizer Timing Optimizations...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/cts/13-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def
[INFO]: Incremented step index to 15.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/cts/spm.resized.v to /openlane/designs/spm/runs/openlane_test/results/routing/spm.resized.v
[INFO]: Incremented step index to 16.
[INFO]: Running Detailed Placement...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def
[INFO]: Incremented step index to 17.
[INFO]: Running Global Routing...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/15-resizer_timing.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Changing layout from 0 to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide to /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide
[INFO]: Current Def is /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def
[INFO]: Current Guide is /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.guide
[INFO]: Incremented step index to 18.
[INFO]: Running Fill Insertion...
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/18-global.def to /openlane/designs/spm/runs/openlane_test/tmp/routing/19-fill.def
[INFO]: Incremented step index to 19.
[INFO]: Writing Verilog...
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/results/routing/spm.resized.v to /openlane/designs/spm/runs/openlane_test/tmp/routing/global.v
[INFO]: Incremented step index to 20.
[INFO]: Running Detailed Routing...
[INFO]: No DRC violations after detailed routing.
[INFO]: Changing layout from /openlane/designs/spm/runs/openlane_test/tmp/routing/19-fill.def to /openlane/designs/spm/runs/openlane_test/results/routing/spm.def
[INFO]: Incremented step index to 21.
[INFO]: Running SPEF Extraction...
[INFO]: Incremented step index to 22.
[INFO]: Running SPEF Extraction...
[INFO]: Incremented step index to 23.
[INFO]: Running SPEF Extraction...
[INFO]: Incremented step index to 24.
[INFO]: Running Static Timing Analysis...
[INFO]: Incremented step index to 25.
[INFO]: Running Static Timing Analysis...
[INFO]: Incremented step index to 26.
[INFO]: Writing Powered Verilog...
[INFO]: Incremented step index to 27.
[INFO]: Writing Verilog...
[INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is.
[INFO]: Changing netlist from /openlane/designs/spm/runs/openlane_test/tmp/routing/global.v to /openlane/designs/spm/runs/openlane_test/results/routing/spm.powered.v
[INFO]: Incremented step index to 28.
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDS II...
[INFO]: Running Klayout to re-generate GDS-II...
[INFO]: Incremented step index to 29.
[INFO]: Streaming out GDS II...
[INFO]: Back-up GDS-II streamed out.
[INFO]: Incremented step index to 30.
[INFO]: Running XOR on the layouts using Klayout...
[WARNING]: /openlane/designs/spm/runs/openlane_test/results/finishing/spm.klayout.gds wasn't found. Skipping GDS XOR.
[INFO]: Incremented step index to 31.
[INFO]: Running Magic Spice Export from LEF...
[INFO]: No illegal overlaps detected during extraction.
[INFO]: Incremented step index to 32.
[INFO]: Running LEF LVS...
[INFO]: /openlane/designs/spm/runs/openlane_test/results/finishing/spm.spice against /openlane/designs/spm/runs/openlane_test/results/routing/spm.powered.v
[INFO]: No LVS mismatches.
[INFO]: Incremented step index to 33.
[INFO]: Running Magic DRC...
[INFO]: Converting Magic DRC Violations to Magic Readable Format...
[INFO]: Converting Magic DRC Violations to Klayout XML Database...
[INFO]: Converting DRC Violations to RDB Format...
[INFO]: Converted DRC Violations to RDB Format
[INFO]: No DRC violations after GDS streaming out.
[INFO]: Running Antenna Checks...
[INFO]: Incremented step index to 34.
[INFO]: Running OpenROAD Antenna Rule Checker...
[INFO]: Incremented step index to 35.
[INFO]: Running CVC
[INFO]: Calculating Runtime From the Start...
[INFO]: Saving Runtime Environment
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: spm
Run Directory: /openlane/designs/spm/runs/openlane_test
----------------------------------------

Magic DRC Summary:
Source: /openlane/designs/spm/runs/openlane_test/reports/finishing/drc.rpt
Total Magic DRC violations is 0
----------------------------------------

LVS Summary:
Source: /openlane/designs/spm/runs/openlane_test/logs/finishing/33-spm.lvs.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------

Antenna Summary:
Source: /openlane/designs/spm/runs/openlane_test/reports/finishing/antenna.rpt
Number of pins violated: 0
Number of nets violated: 0
[INFO]: check full report here: /openlane/designs/spm/runs/openlane_test/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
Basic test failed