Yes you always want to do it post cts open-source-silicon #openlane

Channels

hdl21

unic-cass-23

events

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

dynamic-power-estimation

fossee-iitb-google-sky130

coalition-for-digital-environmental-sustainability

vlsi101

magical

vlsi_verilog_using_opensource_eda

basebands

vlsi_verilog_using_opensoure_eda

digital-electronics-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

generative-ai-silicon-challenge

community_denmark_dtu

Title

Matt Liberty

02/21/2022, 9:27 PM

Yes you always want to do it post cts

Anton Blanchard

02/21/2022, 10:00 PM

We aren't setting it for the STA done in the routing step. Part of the problem is we sometimes call STA with

RUN_STANDALONE=1

and sometimes we dont. @User any idea why?

I presume that's just to get it logged to a separate file?

https://github.com/The-OpenROAD-Project/OpenLane/pull/946 makes sure we always call

set_propagated_clock[all_clocks]

after CTS. I put it immediately after `read_sdc`to make it obvious. run_sta (ie

STANDALONE=1

) is still broken however.

🌏 1