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#openlane
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# openlane
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Mayank Gupta

02/22/2022, 9:45 AM
Getting started with openlane anyone? I wanna design a 2 bit delta Sigma modulator. All i have is experience with sky130 and Xschem with Ngspice. What changes in the flow? Do i have to create a schematic in Xschem and then extract the Verilog code?? Idk. Can someone help me with what is the flow i would be looking at ?
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Vijayan Krishnan

02/22/2022, 9:51 AM
@User yes verilog code enough to start openlane
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Mayank Gupta

02/22/2022, 9:53 AM
Thanks, One thing was bugging me, in mixed signal let's suppose I have a Verilog code as well as a design in transistor level for analog stuff. How does that work with openlane? Can I just integrate both together?
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Vijayan Krishnan

02/22/2022, 9:56 AM
Currently openlane supports digital block only.
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Mayank Gupta

02/22/2022, 9:57 AM
So how is it mixed signal then 🤔
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Vijayan Krishnan

02/22/2022, 10:02 AM
Use openlane for digital block hardening and use https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst caravel for analog part
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Arman Avetisyan

02/22/2022, 10:31 AM
As it is mixed signal, I recommend doing following: 1. Make verilog of digital part, verify it using iverilog 2. Run openlane to get GDS + SPICE 3. Make analog parts as was described in analog design answer of your question. 4. Use caravan (user_analog wrapper) and make a GDS and SPICE that connects the digital and analog parts. For spice you can use Xschem for more visual stuff. 5. pass precheck, send it to efabless
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Mayank Gupta

02/22/2022, 10:37 AM
@User Thanks, i will try this for sure.
@User Thanks, that makes things clear