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Title
j
Jure Vreča
03/17/2022, 4:07 PMHey guys, do you have any tips on dealing with routing congestion problems? I am attaching the error I am getting. As a bit of context I am trying to harden a very simple SoC, which consists of 2 1-kbyte SRAM blocks and a simple risc-v core. I am also attaching the config.tcl file. Any help is appreciated.
m
Matt Venn
03/17/2022, 4:31 PMcan you show the floorplan?
j
Jure Vreča
03/17/2022, 4:40 PMI am attaching the run directory.
m
Matt Venn
03/17/2022, 4:43 PMhow are you placing the macros?
I can't see from the run
macro.cfg doesn't seem to get included
this is the pdn
image.png
but I don't see where the 2 sram would go
another thing to konw is that you can't put sram inside your project, they have to be on the top level
j
Jure Vreča
03/17/2022, 4:44 PMI am not placing them, I thought they will be placed automatically
m
Matt Venn
03/17/2022, 4:44 PMthis is due to limitations in the PDN
no they won't get placed
j
Jure Vreča
03/17/2022, 4:44 PMah. So i have to put it in the user_project_wrapper?
m
Matt Venn
03/17/2022, 4:45 PMso you are just trying to harden the riscv cpu here?
j
Jure Vreča
03/17/2022, 4:45 PMno
I was trying to harden the cpu and also add the srams
I don't understand the reason for why they are two folders: user_proj_example and user_project_wrapper. Is it ok if I just delete the user_proj_example and move everything too user_project_wrapper?
m
Matt Venn
03/17/2022, 4:47 PMuser_proj_example is a dmeo project
you can use it as a template
you can't put anything in user_project_wrapper that needs to be synthesised, only already hardened macros
j
Jure Vreča
03/17/2022, 4:48 PMah
m
Matt Venn
03/17/2022, 4:48 PMso you need to harden your riscv as one block, then connect it up to 2 sram blocks in user project wrapper
j
Jure Vreča
03/17/2022, 4:48 PMso I should put the risc-v core in the user_project_example and put the sram in the wrapper
I see, Thank you for that info. Ill try that now.
m
Matt Venn
03/17/2022, 4:50 PMif you are new to the tools, I might advise you to simplify your goal
here's my application that uses sram
and there are lots of workarounds to get it to work, including turning off drc checking and obstruction layers
j
Jure Vreča
03/19/2022, 12:29 PMHey Matt, sorry the reply is so late, I was traveling yesterday and didn't find the time to try your advice out. But today I did, and I separated the risc-v core in to a the user_project_example. This fixed the original routing problem, but the router now still fails to complete, and the error is not very descriptive. I am attaching a picture of the error as well as the issue reproducible zip. Also the github link: https://github.com/jurevreca12/rvj1-caravel-soc/ , contains the latest design. I will be very grateful for any help.
I am also attaching the lower part of the error output.
image.png
After some googling I realized that the issue I am having is the same as https://github.com/The-OpenROAD-Project/OpenLane/issues/996 . After updating my openlane version, I get the same stack trace output as in the git link.