Hello, has anyone tried synthesizing an asynchronous design using openlane? In my case, openlane hangs at report_power. If I disable the power report( by commenting it out in sta.tcl ) it then hangs when generating the PDN. I have tried the following workaround, but it doesn't seem to change anything (https://github.com/The-OpenROAD-Project/OpenLane/issues/64). The rtl simulation works fine. Link to the openlane script: https://github.com/6Kotnk/caravel_example/blob/test/openlane/user_project_wrapper/config.tcl Any help would be appreciated.

I’ve gotten some asynchronous designs all the way through to gds. For example this verilog output from the demo of petrify [1] worked just fine all the way through the flow. module pn_synthesis_net (a, _reset, b, e, f); input a; input _reset; // Reset pin active at low output b; output e; output f; wire c; assign b = ~a & c | a & ~e; assign e = ~a & c | f & a; assign f = ~a & b | a & e; assign c = _reset & (~a & b | a & ~e); // Initial state: // !a !b !e !f !c endmodule All I had to do was tell openlane that _reset was the clock net, although I did spec a pretty long period in the sdc for more complex designs. But in the end everything was happy. That does mean _reset gets a clock tree, but for this design style that’s not necessarily a bad thing. [1] https://www.cs.upc.edu/~jordicf/petrify/refs/

pdn doesn't care about whether you are synchronous or not so something else is going on. An issue with a test case would be helpful

@User Check your openlane/user_proj_example/runs/RUN_tag/openroad_issue_reproducible directory and zip and attach here or file a github issue here: https://github.com/The-OpenROAD-Project/OpenLane/issues

Thanks for the replies. I've tried setting the reset as the clock net (with a long period) but the problem persists.

set ::env(FP_PDN_IRDROP) 0

set this in

config.tcl

and try