I’ve gotten some asynchronous designs all the way through to gds.
For example this verilog output from the demo of petrify [1] worked just fine all the way through the flow.
module pn_synthesis_net (a, _reset, b, e, f);
input a;
input _reset; // Reset pin active at low
output b;
output e;
output f;
wire c;
assign b = ~a & c | a & ~e;
assign e = ~a & c | f & a;
assign f = ~a & b | a & e;
assign c = _reset & (~a & b | a & ~e);
// Initial state:
// !a !b !e !f !c
endmodule
All I had to do was tell openlane that _reset was the clock net, although I did spec a pretty long period in the sdc for more complex designs. But in the end everything was happy. That does mean _reset gets a clock tree, but for this design style that’s not necessarily a bad thing.
[1]
https://www.cs.upc.edu/~jordicf/petrify/refs/