Hello, I am trying to synthesize my design using o...
# openlane
Hello, I am trying to synthesize my design using openlane, and I am getting an error in placement. In the added picture you can see the log: "12-opendp.log". The design is an SoC containing a simple risc-v core, and only 1 kByte of instruction RAM (I temporarily removed the dataram because I could'nt get through placement). The link to the openlane script is here: https://github.com/jurevreca12/rvj1-caravel-soc/blob/develop/openlane/user_proj_example/config.tcl, and that repo also contains the entire project. What am I doing wrong? Also why can't I get the placement to finnish when I add more then 1kbyte of RAM? I mean I see that there is an openram_testchip that contains several 8kByte SRAM blocks, so I have no idea why my design doesn't go through.
generated during run time inside
where can I find it?
Hey, Viljayan, I attached the folder here.
I just noticed I spelled your name wrong Vijayan, sorry about that.
I am not facing any issue with
with your DB
hm. So maybe then my openlane version could be problematic?
try re-run again
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openroad> if { [info exists ::env(PL_OPTIMIZE_MIRRORING)] && $::env(PL_OPTIMIZE_MIRRORING) } {
...>     optimize_mirroring
...> }
[INFO DPL-0020] Mirrored 2694 instances
[INFO DPL-0021] HPWL before          324500.2 u
[INFO DPL-0022] HPWL after           319554.4 u
[INFO DPL-0023] HPWL delta               -1.5 %
openroad> if { [catch {check_placement -verbose} errmsg] } {
...>     puts stderr $errmsg
...>     exit 1
...> }
I re-ran it several times. I ran now make user_proj_example > log.txt and I am uploading the log file here. I do get warning about versions of tools and open_pdks, but I am not really sure where this comes from since I installed the pdks using make pdk-with_sram command.
Plz update your caravel repo and openlane tool according to mpw-5c
@User Since I recently taped out a project that has both 1kB and 2kB SRAMs, I had a look at your project. You seem to be including the OpenSRAM macros from your user_project rather than from the user_project_wrapper, as the currently successfully taped out projects https://platform.efabless.com/projects/680 and https://platform.efabless.com/projects/745 do. Perhaps doing that as well may be a circumvention of your problem. Your user_project also has a configured size of 900x600 (micrometers is the unit, I think), while the OpenSRAM macros you are using have sizes of 680x414 and 476x395. They will not both fit into 900x600 no matter how they are placed. And if I remember correctly, there have been problems with auto-placing OpenSRAM macros in the past anyway, but I'm not sure if that's still up-to-date. The reason why the Test chip can be placed is that it uses the full user_space_wrapper space, while in your config.tcl for the user_project, where you include the SRAM macros, there is the following line: set ::env(DIE_AREA) "0 0 900 600" It sets the size of the user project macro to 900x600, which is much smaller than the ~2900x3500 of space available.
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I am still using obstructions on all layers for openram to avoid drc issues
@User If you're not sure on how much die area required for design, simply comment line 72 and 73 in your
and proceed with automatic macro placement
I followed your advice and removed the DIE AREA size from config.tcl file. Now the placement is working, but I am having problems with routing. But this is a seperate issue, so thank you for your help.