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#riscv
Title
# riscv
y

yrrapt

07/19/2020, 7:46 AM
AHB and APB would typically be used together with a bridge between. High throughput items like memories would be on AHB and simpler, lower throughpug items like an I2C peripheral on APB. So theres not a clear one or the other between those - usually both. In general you should be able to bridge between multiple buses with varying levels of performance impacts. In my limited opinion its actually easier to get high quality SoC IP in AHB/APB/AXI than Wishbone. The first too because they're dominant buses in commercial SoC world and there's spill over. You can find some high quality IP in the Roa logic and Pulp repositories amongst other places. AXI is the defacto bus protocol in Xilinx 7 series devices so theres a lot of things supporting that - although more on specialist processing blocks (ie. Image processing) than SoC building builds. Finally there's obviously a lot of wishbone IPs out there - but anyone that's tried to use them seriously will tell you that the quality and plug and play compatibility varies wildly. Sometimes you end up wondering why don't just write it from scratch. Sometimes it does just work. My thoughts on the buses. Hope its useful
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ALI AHMED

07/19/2020, 8:46 PM
thanks