it should be faster than the first machine I ran linux on 😉

join #serdes if you are interested in PCIE (pci-e gen1 and gen2 match Infiniband SDR and DDR.. 2.5Ghz and 5ghz respectively)

May be of use for others despite plethora of RV stuff out there: https://github.com/stineje/osu-riscv

just fyi

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RTL2GDS Workshop No. 1/6 - Let's build RISC-V specs and code it in RTL I know you might be thinking, what's the use of this workshop when there are so many free webinars and courses already over the web about RISC-V?   One and only one answer - Your own personalized and structured lab based GitHub repo which gives you direct access to RISC-V recruiters in some of the TOP semiconductor industry. We had participants in past whose GitHub repos are displayed in RISC-V Org and industry has been contacting them directly   Why so? VSD workshops are timeline and deadline based, just like how its in industries. Hence industry like VSD workshop participants, and looking forward to work with them. Their only criteria - strong fundamentals. That's possible only through a structured cloud based labs and our RISC-V labs has been very popular among students (especially freshers), as students love the GitHub and deadline based model   So feel free to experience the same starting 25th August and here's the registration link: https://www.vlsisystemdesign.com/riscv-based-myth/   All the best and happy learning

Free LIVE demo/webinar on below 4 topics tonight at 29th August, 7pm IST 1. Block-Based Circuit Design, Ninad Jangle, mentored by Prof. Gayatri Mehta, University of North Texas 2. Virtual FPGA Lab, Bala Dhinesh, mentored by Akos Hadnagy, former GSoC student 3. RISC-V Tensor Core Extension for Deep Learning, Nitin Mishra, mentored by Theodore Omtzigt, CEO Stillwater Supercomputing 4. RISC-V Many-core Accelerator on Cloud FPGAs, Vineet Jain, mentored by Shivam Potdar, former GSoC student Fill up the form to receive email invitation (Form closes in 6hours which is at 3pm IST) https://www.vlsisystemdesign.com/vsd-intern-free-webinar/ All the best and happy learning

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Hello all, we are trying to use RISC-V to execute a program by reading and writing contents through Wishbone bus. But when we tried to execute wishbone read & write from the Flash memory, it took about 250 cycles of 50MHz clock for each wb_write/read. And then we tried executing the same code from SRAM, and it took about 25 cycles of 50MHz clock for each wb_write/read. I assume that the Flash memory is connected to the processor via an SPI and so time complexity increases for Parallel to serial conversion, but still 250 cycles for one wb_write is so high. Could someone explain the reason for this slow execution of the program?

Popular RISC-V based MYTH workshop is back Despite of having so many free resources on RISC-V microarchitecture design courses around the globe, VSD is proud to say that customers found our paid RISC-V based MYTH (microprocessor for you in thirty hours) 5-day workshop as the most structured one which hand-holds anyone and everyone who wants to learn RISC-V ISA and RISC-V uarch design from scratch. We had examples of 12/13-yr old students taking this workshop. Making workshops or courses free is more challenging as now you would have many eyes viewing your content, and one glitch in delivery might impact your brand. That's the reason, VSD free content and workshops are even more carefully curated. RISC-V based MYTH workshop last day for registration - 29th November, 11:59pm IST, 2021 Workshop dates - 1st - 5th December, 2021 (FYI - There are other Sky130 related workshops in same dates) Registration link - https://www.vlsisystemdesign.com/riscv-based-myth/ Mode of delivery - Workshop is on cloud. So you can login at your convenient time within 5-days, finish lectures/labs for the day and logout Workshop Day wise Content : Day 1 : Introduction to RISC-V ISA and GNU compiler toolchain 1. Introduction to RISC-V basic keywords 2. Labwork for RISC-V software toolchain 3. Integer number representation 4. Signed and unsigned arithmetic operations Day 2: Introduction to ABI and basic verification flow 1. Application Binary interface (ABI) 2. Lab work using ABI function calls 3. Basic verification flow using iverilog Day 3: Digital Logic with TL-Verilog and Makerchip 1. Combinational logic in TL-Verilog using Makerchip 2. Sequential and pipelined logic 3. Validity 4. Hierarchy Day 4: Basic RISC-V CPU micro-architecture 1. Microarchitecture and testbench for a simple RISC-V CPU 2. Fetch, decode, and execute logic 3. RISC-V control logic Day 5: Complete Pipelined RISC-V CPU micro-architecture/store 1. Pipelining the CPU 2. Load and store instructions and memory 3. Completing the RISC-V CPU 4. Wrap-up and future opportunities All the best and happy learning

Exclusive VSD-HDP for Front-end, FPGA, EDA and RISC-V As you know, there are a lot of requests on VSD based Front-end, FPGAs and RISC-V hardware design programs, so here is the list of projects under the exclusive guidance and mentorship of Steve Hoover, Founder of RedWood EDA. Now the word exclusive plays a bigger role here, as the projects listed below are the future of our VLSI industry and getting hold of these projects means you have secured a position in the present and future of the semiconductor industry. Important Note - Interested participants can reply back to this message asking for a detailed description and we will send it across Link for registration - https://www.vlsisystemdesign.com/hdp/ Program start/end date - 2nd January to 13th March, 2022

VSD-HDP : Verilator Verification Environment for RISC-V vector accelerator Now this is how VSD wants to approach design verification - Something new, something exciting, something never done before - Probably, if you are reading this email and would be interested in joining our design verification HDP program, you would be the first one in the whole world (like all VSD interns in past) to do this, may be publish it. Reply back to this email, if you are interested, and we will send you registration/payment link Cohort Starting from Jan 15, 2022 for a duration of 10-weeks Big Picture: There has been, for about a year, an activity to try to work on a RISC-V vector accelerator that is tailored to be able to execute machine learning workloads. And there is one innovation that we are trying to do that nobody else in the world does and that is to implement an instruction called fused dot-product. A fused dot-product is a mechanism to introduce user-defined rounding in arithmetic. And if you do that, then what you gain is you are able to do smaller representations for the weights in the ML model. If we look at a traditional linear algebra execution engine, it will use a dot-product, but it will use a fused multiply-add. And if you do that then every sum of the “sum of products” that dot-product exists will have a rounding event. If we have a large matrix, which is typical in a machine learning environment, you have millions of rounding errors. And the reason this is a problem for machine learning is that the matrices that are being used are such that they tend to be multi-modal. What it really means (from a numerical point of view) is that you have multiple peaks of energy that you are trying to resolve. And if you have rounding error, you will have one of these peaks basically attenuate to a point where it is no longer resolvable This is what fused dot-product is solving From a verification point of view, the real fun starts in the fact that we are going to bring in different arithmetic. We could bring in IEEE, we could bring in bfloat from Google, we could bring Microsoft fp9 or we can bring in the number system called posit, which is a tapered floating point. There is research out there which people have done where they have demonstrated an 8-bit posit can compete with single precision IEEE floating point in these machine learning applications, if you use fused dot-product – That is the context of the project Project description: As you can imagine, there is close to 7000+ blocks that are of interest here that have their own complexity and need The project which we are starting here is really to try to build a testbench and verification strategy that would allow us to, progressively over time, add these blocks that are of importance We will start off with an integer ALU, not very much complexity in that, but it gives you a vehicle to start thinking about the whole verification strategy. One of the things we are trying to do is adhere to opensource strategy, so that anybody can pick up this GitHub repo and be productive with this, without needing industrial tools. And one vehicle which is industrial strength for verification is Verilator In a nutshell, the project really is to build a Verilator Verification environment i.e. a structure in which we can set up testbenches that are executed with Verilator. The thing which is interesting in this project is we are going to tie that Verilator piece with a golden model arithmetic library and that is going to be something that you can publish as nobody else in the world has that It’s a Verilator Testbench environment that uses an online arithmetic library to generate the right bit pattern. We are not using randoms, but we are using a Golden model. If you progress from ALU to a vector accelerator, you will have a vector lane, vector register file, vector load/store unit, vector instructions. We can layer this testbench in such a way that when a new project resource comes online and needs to implement (for eg.) vector scale instruction, then there is a reusable testbench structure which that person can quickly pick-up, set as their basic structure, build their functionality into it, and have a working testbench environment in which they can test their work First Steps: First round of HDP will be a testbench which is driven purely by a C++ verilog testbench that brings in the golden model. This is the first step in which you take a verilog module that is a transformation of some sort, and you tie that into a Verilator testbench that can drive that module and that can also drive the golden result. So, this is Verilator specific in the sense that Verilator is really the main function of C++ program. And when you bring in a verilog module, that gets transformed into a C++ code that then gets driven by the main function of Verilator. There are 2 problem statements here One is to setup the environment so that you have the right Makefile, you have the right structure which you can expand to new functional units Second is how to link in the golden model     Summary of Project execution: 1.     Articulate a productive organization in which testbenches are built 2.     Then we need a productive Makefile that a programmer or designer can simply say “make test” and you have the test environment 3.     Then we need to have integration with the golden model which brings in new GitHub repo and that machinery needs to be figured out

I've added a pull request on the

dockerized-verification-setup

repo which significantly reduces the size of the docker file. I would appreciate if someone could review and merge please

Also, in a somewhat related manor, on the

mpw-5b

tag the makefile

env.makefile

specifies that

GCC_PREFIX=riscv32-unknown-linux-gnu

which has changed from generating bare metal images, is there any reason for this change?

@User You probably want to ask in #C016H8WJMBR or #C016G7Z8GDR - Unsure if the developers at efabless will see the requests here

Hi again all, is there any documentation for the CPU memory layout and implementation for the Caravel SoC? The linker script has changed quite a lot and it's no longer clear to me where sections should be placed. Has anyone seen a diagram?

A brilliant initiative by OSFPGA Foundation toward learning VSD has worked with many organizations globally, but working with OSFPGA was a unique experience. One of the prime reasons for this successful engagement could be because of its "torchbearers" Dr Shrikant Lohokare and Dr Naveed Sherwani. Dr Shrikant holds a doctorate from the University of Illinois, Urbana-Champaign and Dr Naveed received PhD. from the University of Nebraska-Lincoln. With such rich profiles, their interest in learning initiatives is quite evident. So here's the announcement. OSFPGA, along with VSD, are excited to provide a full-stack overview of RISC-V on FPGA and OpenFPGA courses at more than 55% discounted price than its original price, in the spirit of talent generation. Here's the link which has all 3-workshops https://osfpga.org/osfpga-training/ OSFPGA is determined to bring many students, colleges and start-ups on board and democratize hardware design. So OSFPGA, in association with VLSI System Design (VSD) and Redwood EDA, presents a complete stack of overview courses starting from RISC-V ISA, moving on to RISC-V micro-architecture implementation from scratch then building mixed-signal design using RISC-V and implementing on commercial FPGA and finally porting RISC-V on OpenFPGA. The whole course is divided into 3 sub-courses 1. RISC-V based MYTH (Microprocessors for you in thirty hours) (5-day course) (25th May to 29th May) 2. Mixed-signal RISC-V based SoC on FPGA (1-day course) (30th May) 3. FPGA – Fabric, Design and Architecture (5-day course) (1st June to 5th June) For the first time, cloud-based RISC-V on FPGA workshops has been available at such low cost, just for the spirit of learning, thereby providing an affordable platform to the bright, young, talented workforce who would be the future torchbearers of the semiconductor industry That's the best we can do in terms of pricing. So grab this limited time OSFPGA sponsored pricing on all the above workshops. All the best and happy learning -- Thanks & Regards Kunal P Ghosh "_*A pessimist always sees difficulty in every opportunity, An optimist always sees opportunity in every difficulty*_"

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Hi all, Recently we are trying to utilize the riscv-dv utility provided by google to obtain a randomized assembly sequence for testing purposes of our design Can anyone provide some insight to this specific issue on setting riscv-dv on their setup? https://github.com/google/riscv-dv/issues/905 (Similar issues are also seen but no clear solutions are found as of yet) Thanks!

To view this discussion on the web visit https://groups.google.com/d/msgid/unum-computing/7FBE2B07-320B-45B9-AA87-66CF3D62C5E9%40earthlink.net.

Posted in #openpositarithmetic

i am trying to program my Arty-7 A35T FPGA using OLIMEX-ARM-USB-TINY-H, can I do this or not? If yes then How?

I managed to setup rust for the Caravel vex core and get pure rust-blinky to work!

and the obligatory waveform:

image.png

https://arxiv.org/pdf/2305.06946.pdf May 2023 Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing David Mallase ́n, Alberto A. Del Barrio, _Senior Member, IEEE _and Manuel Prieto-Matias *Abstract*—The accuracy requirements in many scientific computing workloads result in the use of double-precision floating-point arithmetic in the execution kernels. Nevertheless, emerging real-number representations, such as posit arithmetic, show promise in delivering even higher accuracy in such computations. In this work, we explore the native use of 64-bit posits in a series of numerical benchmarks extracted from the PolyBench collection and compare their timing performance, accuracy and hardware cost to IEEE 754 doubles. For this, we extend the PERCIVAL RISC-V core and the Xposit custom RISC-V extension with posit64 and quire operations. Results show that posit64 can execute as fast as doubles, while also obtaining up to 4 orders of magnitude lower mean square error and up to 3 orders of magnitude lower maximum absolute error. However, leveraging the quire accumulator register can limit the order of some operations such as matrix multiplications. Furthermore, detailed FPGA synthesis results highlight the significant hardware cost of 64-bit posit arithmetic and quire. Despite this, the large accuracy improvements achieved with the same memory bandwidth suggest that posit arithmetic may provide a potential alternative representation for scientific computing. *Index Terms*—Arithmetic, Posit, IEEE-754, Floating point, Scientific computing, RISC-V, CPU, Matrix multiplication, PolyBench. Slack Conversation

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