Rae Parnmukh

07/19/2020, 6:04 PM
@User if you can determine your peripherals that can be the start point to define the protocols. Similar to what @User describes. If you get a Xilinx prototyping board that would come with some basic peripherals and interface drivers, you could check out the vcu707 or vcu118 depending on your project size.


07/19/2020, 8:58 PM
Hi @Rae Parnmukh, @yrrapt thanks for your input, We are looking at RV32IMC core with seperate ICCM and DCCM, that can run on Xilinx arty board with peripherals including GPIOs, UART, I2C, QSPI (for external flash interface) . Right now we are not interested in Caches. We want to add a debug unit with associated machine mode CSRs. What should be the best target bus architecture for above peripherals. One solution is using AHB or AXI for connecting RV32IMC , ICCM , DCCM, flash controller along with APB bridge to peripherals. Are they Ok for ASIC tapeout used in shuttle program for 130nm design or should i use wishbone\?