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#riscv
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# riscv
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Adrian Freed

07/19/2020, 5:21 AM
Hi @User. In my searches I found that there is a lot of open licensed IP for peripherals on wishbone.
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ALI AHMED

07/19/2020, 5:30 AM
So, should we go for Wishbone B4? so it will allow us to use that open licensed IP peripherals.
Thanks for suggestion @Adrian Freed
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Adrian Freed

07/19/2020, 5:45 AM
This study compares buses for Open Core use: http://cdn.opencores.org/downloads/soc_bus_comparison.pdf . Note that the open source cores I found are in a variety of languages and with different flows, VHDL, Verilog, Scala - to name a few. Your decision may want to also be based on what you want to put on the bus and the shortest path to that IP. I got briefly excited about a Lattice Verilog example and then discovered I couldn’t look at it without promising to only run it on Lattice FPGAs. This was a good reminder to me to look carefully at the license details: “free” and “open” are subject to interpretation.
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ALI AHMED

07/19/2020, 8:00 PM
thanks @Adrian Freed, very useful
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