open-source-silicon.dev

powered_verilog_error.png

<@U016EM8L91B> <@U017X0NM2E7> I am using vlog2Verilog and I passed lef file as a parameter to -l , but the sky130_fd_sc_hvl cells does not show VPWR or VPB in generated verilog.

<https://github.com/The-OpenROAD-Project/OpenLane/blob/cbb9e6b02aff0e064e65bd6651157693576de3d8/docs/source/usage/advanced_power_grid_control.md#core-level|https://github.com/The-OpenROAD-Project/OpenLane/blob/cbb9e6b02aff0e064e65bd6651157693576de3d8/docs/source/usage/advanced_power_grid_control.md#[…]l>

I am using standalone vlog2Verilog. I wanted to convert a generated 1_synth.v from ORFS flow to powered verilog.

Sorry, not familiar with the program. Where's is it installed?

<https://github.com/RTimothyEdwards/qflow/tree/master/src>

Is qflow included in openlane or does it have to be installed independently?

No I don't think it is included in openlane. It needs to be installed independently

v2v.png

I can see vlog2Verilog in under OpenLane/dependencies/tools_metadata.yml

<@U017X0NM2E7>:  The openlane developers were looking for a way to insert power connections back into a verilog gate-level netlist, and I suggested `vlog2Verilog`, which I wrote for that purpose.  <@U021BTRSZ5H>:  What is your command line invocation of vlog2Verilog?  There are a number of parameters that need to be passed.  Since it was used internally by qflow, I don't know how obvious the parameters and syntax are for use outside of qflow, but I think it should work.

<@U016EM8L91B> The command was:
. /vlog2Verilog 1_synth.v -o 1_synth_power.v -l /home/pranav/OpenROAD-flow-scripts/flow/platforms/sky130hvl/lef/sky130_fd_sc_hvl.lef

<@U016EM8L91B>  Is this the correct usage for vlog2Verilog??

<@U021BTRSZ5H>:  You may need an additional `-l` option to read the technology LEF file (before the standard cell LEF), and you may need to specify `-v "VPWR,VPB" -g "VGND,VNB"` .  There may be issues with the level shifter cells in the HVL library because they have multiple power supplies, and I do not think I have ever run vlog2Verilog on the Sky130 HVL library.  So let me know if there are issues.

pt_cell.png

cap_lef.png

<@U016EM8L91B> Yes! I had figured that I need to specify -v and -g . The standard cells showed correct connections. But for other blocks it adds or does not add some power connections.

Here for cap it adds second vgnd and vpwr which not in the lef file. And for PT_UNIT_CELL it does not add vpwr which is defined in lef

capacitor_test_nf.lef

PT_UNIT_CELL.lef

I guess the issue with the PT_UNIT_CELL is related with what you said above about the multiple power supplies.

Also the script was written as part of a digital flow, where every cell was assumed to have the same power connections.