1. Part of your report is being truncated. Try

export NETGEN_COLUMNS=80

before LVS. 2. The nfet looks like it’s an extracted parameterized cell. Are you running from a

mag

file or gds?

i'm running from magic

It doesn’t look like you have mosfet source/drain swapping enabled. Are you using

$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl

? Could you share your LVS command?

I did netgen in the terminal to open up netgen

then I did lvs "mpw8.spice mpw8" "mpw8_mag.spice mpw8_mag"

I think I have to include the setup script somehow

lvs "mpw8.spice mpw8" "mpw8_mag.spice mpw8_mag" <setup_file>

Replace

<setup_file>

with the full path to the setup file.

ok, is there a way to keep all the commands in a text file so I don't have to type them out

image.png

so I tried both fixes, I'm still getting stuff like this

image.png

what is proxygpio?

I'm still getting weird errors where it says two things are different when they are the same, and I think it might be due to the pins not matching?

I manually went through my LVS report and checked all the errors, and the left side seems to always match with the right side for all of them

Hi there, does anyone know what - "Can't find a schematic counterpart for top cell - use 'same_circuit' to establish a correspondence" error means

@Tim Edwards Running LVS on slot-036 of MPW-2. The

user_proj_example

has the following assign statements for top level signals.

assign la_data_out[27] = io_out[35];
   assign la_data_out[26] = io_out[34];
   assign la_data_out[25] = io_out[33];
   assign la_data_out[24] = io_out[32];
   assign la_data_out[23] = io_out[31];
   assign la_data_out[22] = io_out[30];
   assign la_data_out[21] = io_out[29];
   assign la_data_out[20] = io_out[28];
   assign la_data_out[19] = io_out[27];
   assign la_data_out[18] = io_out[26];
   assign la_data_out[17] = io_out[25];
   assign la_data_out[16] = io_out[24];
   assign la_data_out[15] = io_out[23];
   assign la_data_out[14] = io_out[22];
   assign la_data_out[13] = io_out[21];
   assign la_data_out[12] = io_out[20];
   assign la_data_out[11] = io_out[19];
   assign la_data_out[10] = io_out[18];
   assign la_data_out[9] = io_out[17];
   assign la_data_out[8] = io_out[16];
   assign la_data_out[7] = io_out[15];
   assign la_data_out[6] = io_out[14];
   assign la_data_out[5] = io_out[13];
   assign la_data_out[4] = io_out[12];
   assign la_data_out[3] = io_out[11];
   assign la_data_out[2] = io_out[10];
   assign la_data_out[1] = io_out[9];
   assign la_data_out[0] = io_out[8];
   assign io_oeb[35] = io_oeb[10];
   assign io_oeb[34] = io_oeb[10];
   assign io_oeb[33] = io_oeb[10];
   assign io_oeb[32] = io_oeb[10];
   assign io_oeb[31] = io_oeb[10];
   assign io_oeb[30] = io_oeb[10];
   assign io_oeb[29] = io_oeb[10];
   assign io_oeb[28] = io_oeb[10];
   assign io_oeb[27] = io_oeb[10];
   assign io_oeb[26] = io_oeb[10];
   assign io_oeb[25] = io_oeb[10];
   assign io_oeb[24] = io_oeb[10];
   assign io_oeb[23] = io_oeb[10];
   assign io_oeb[22] = io_oeb[10];
   assign io_oeb[21] = io_oeb[10];
   assign io_oeb[20] = io_oeb[10];
   assign io_oeb[19] = io_oeb[10];
   assign io_oeb[18] = io_oeb[10];
   assign io_oeb[17] = io_oeb[10];
   assign io_oeb[16] = io_oeb[10];
   assign io_oeb[15] = io_oeb[10];
   assign io_oeb[14] = io_oeb[10];
   assign io_oeb[13] = io_oeb[10];
   assign io_oeb[12] = io_oeb[10];
   assign io_oeb[11] = io_oeb[10];
   assign io_oeb[9] = io_oeb[10];
   assign io_oeb[8] = io_oeb[10];

This results in shorts between pins at the top level. To prevent magic from deleting the shorted pins, I’m using

ext2spice short resistor

This preserves all the pins in the layout, but still getting these messages (maybe from verilog?)

Duplicate pin io_oeb[34] in cell user_project_wrapper
Duplicate pin la_data_out[27] in cell user_project_wrapper
Duplicate pin la_data_out[26] in cell user_project_wrapper
Duplicate pin la_data_out[25] in cell user_project_wrapper
Duplicate pin la_data_out[24] in cell user_project_wrapper
Duplicate pin la_data_out[23] in cell user_project_wrapper
Duplicate pin la_data_out[22] in cell user_project_wrapper
Duplicate pin la_data_out[21] in cell user_project_wrapper
Duplicate pin la_data_out[20] in cell user_project_wrapper
Duplicate pin la_data_out[19] in cell user_project_wrapper
Duplicate pin la_data_out[18] in cell user_project_wrapper
Duplicate pin la_data_out[17] in cell user_project_wrapper
Duplicate pin la_data_out[16] in cell user_project_wrapper
Duplicate pin la_data_out[15] in cell user_project_wrapper
Duplicate pin la_data_out[14] in cell user_project_wrapper
Duplicate pin la_data_out[13] in cell user_project_wrapper
Duplicate pin la_data_out[12] in cell user_project_wrapper
Duplicate pin la_data_out[11] in cell user_project_wrapper
Duplicate pin la_data_out[10] in cell user_project_wrapper
Duplicate pin la_data_out[9] in cell user_project_wrapper
Duplicate pin la_data_out[8] in cell user_project_wrapper
Duplicate pin la_data_out[7] in cell user_project_wrapper
Duplicate pin la_data_out[6] in cell user_project_wrapper
Duplicate pin la_data_out[5] in cell user_project_wrapper
Duplicate pin la_data_out[4] in cell user_project_wrapper
Duplicate pin la_data_out[3] in cell user_project_wrapper
Duplicate pin la_data_out[2] in cell user_project_wrapper
Duplicate pin la_data_out[1] in cell user_project_wrapper
Duplicate pin la_data_out[0] in cell user_project_wrapper

and LVS yields a matching topology with pin mismatches.

(no matching pin)       |io_oeb[35]                  
(no matching pin)       |io_out[35]                  
(no matching pin)       |io_out[34]                  
(no matching pin)       |io_out[33]                  
(no matching pin)       |io_out[32]                  
(no matching pin)       |io_out[31]                  
(no matching pin)       |io_out[30]                  
(no matching pin)       |io_out[29]                  
(no matching pin)       |io_out[28]                  
(no matching pin)       |io_out[27]                  
(no matching pin)       |io_out[26]                  
(no matching pin)       |io_out[25]                  
(no matching pin)       |io_out[24]                  
(no matching pin)       |io_out[23]                  
(no matching pin)       |io_out[22]                  
(no matching pin)       |io_out[21]                  
(no matching pin)       |io_out[20]                  
(no matching pin)       |io_out[19]                  
(no matching pin)       |io_out[18]                  
(no matching pin)       |io_out[17]                  
(no matching pin)       |io_out[16]                  
(no matching pin)       |io_out[15]                  
(no matching pin)       |io_out[14]                  
(no matching pin)       |io_out[13]                  
(no matching pin)       |io_out[12]                  
(no matching pin)       |io_out[11]                  
(no matching pin)       |io_out[10]                  
(no matching pin)       |io_out[9]                   
(no matching pin)       |io_out[8]                   
io_oeb[35]              |(no matching pin)           
io_out[35]              |(no matching pin)           
io_out[34]              |(no matching pin)           
io_out[33]              |(no matching pin)           
io_out[32]              |(no matching pin)           
io_out[31]              |(no matching pin)           
io_out[30]              |(no matching pin)           
io_out[29]              |(no matching pin)           
io_out[28]              |(no matching pin)           
io_out[27]              |(no matching pin)           
io_out[26]              |(no matching pin)           
io_out[25]              |(no matching pin)           
io_out[24]              |(no matching pin)           
io_out[23]              |(no matching pin)           
io_out[22]              |(no matching pin)           
io_out[21]              |(no matching pin)           
io_out[20]              |(no matching pin)           
io_out[19]              |(no matching pin)           
io_out[18]              |(no matching pin)           
io_out[17]              |(no matching pin)           
io_out[16]              |(no matching pin)           
io_out[15]              |(no matching pin)           
io_out[14]              |(no matching pin)           
io_out[13]              |(no matching pin)           
io_out[12]              |(no matching pin)           
io_out[11]              |(no matching pin)           
io_out[10]              |(no matching pin)           
io_out[9]               |(no matching pin)           
io_out[8]               |(no matching pin)

These pins should match, as far as I can tell. This output is from netgen’s

MatchPins

routine after printing the matching pins. So maybe the deleted pins are causing the routine to stop before it should. I’ll look into it a little more, but would welcome any advice. I think that ideally, LVS should not delete shorted pins, but rather check that all pins are shorted in the same manner in both the layout and source. (The

user_proj_example

level does not have text, so extracting the gds, as is, isn’t very helpful. I flattened

user_proj_example

in the

user_project_wrapper

layout, but when running LVS, netgen takes 8 hours to flatten the verilog side of

user_proj_example

. Since the verilog top is just a wrapper, I replaced the

user_proj_example

call in

user_project_wrapper

with the actual contents of

user_proj_example

and netgen runs in about 5 mins.)

Hi all, I am trying to get familiar with the opensource process flow, so I am running through all the tools with a simple inverter I made. Currently I am stuck on getting LVS to pass. The issue I am running into is a netlist mismatch between my inverter schematic (4 nets) and my inverter layout (6 nets). I imported the spice file of my inverter into Magic, and it placed all the cells and pins, so I just routed everything together. Once I had everything routed I ran the following to extract the layout:

extract all
ext2spice lvs
ext2spice

Once this is done I open netgen and run the following command:

lvs "inv.spice inv" "inv_mag.spice inv_mag" sky130A_setup.tcl

I figure I am doing something wrong when I create my layout, but I am not able to pinpoint what it is. I've attached an image of my layout along with the spice files and the comp.out file. I appreciate any help on this issue. Thanks!

Hello everyone. Hope you're doing well. I'm doing LVS of a circuit that includes resistors, but it seems like there might be an error related to them. Does anyone have any thoughts on this issue?

@Mitch Bailey Excuse me. can you guide me to know how to fix the lvs , please? Note: 1) i usually use an attached simple script to match the generated files from scheme and magic.

op_lvs_iamip123.py

@Sam Ellicott has left the channel

Hi @Tim Edwards @Mitch Bailey Excuse me, can you guide me to know how to fix this lvs , please? Note: 1-The extracted spice file is simulated successfully. 2-Get spice file from MAGIC using

gds read <cell>

flatten -doinplace dac_3v_8bit

extract do local

extract all

ext2spice lvs

ext2spice

Thanks.

Hi, I I tried layout opamp and failed on lvs. Perhaps the problem occurred because the number of transistors did not match with using the nf parameter. Is there any netgen option for this?

opamp.sp

: pre-layout file

opamp.spice

: post-layout file

@Tim Edwards On a couple of the analog designs (slot-020 and slot-021) for mpw-3, there were unexpected shapes on the resistor recognition layers. This probably extracts to sizes that don’t represent the actual layout. Is there a way in drc or extraction to flag non-rectilinear resistors?

For metal resistors, I was thinking of detecting them as shorts and generating a short-type ideal resistor with zero ohms (extresist could split the difference and add to each side).

For metal short resistors, the size is probably not important. In the above layouts, red is poly and green is ndiffusion.

@Mitch Bailey: It would be an error, essentially, to draw a poly or diffusion resistor that way, so I'm not too worried about trying to make the L and W calculation work out correctly for those cases.

Hi @Tim Edwards @Mitch Bailey Can you please guide to check the source of mismatch her? I used the following commands to generate the spice file from the layout

select top cell

flatten -doinplace dac_3v_8bit_0

flatten -doinplace sbamuxm4_0

extract do local

extract all

ext2spice lvs

ext2spice

Thanks in advance

I am doing

model *cell_name* blackbox

to mark a subcircuit as blackbox in netgen lvs setup.tcl script and I can confirm with

puts [model *cell_name*]

that the model type for cell_name changes from subcircuit to blackbox. But then in the lvs report I see it is still comparing them as subcircuits (and thus failing lvs because they don't match, hench why I want to make them black box)... I'm not sure I understand how to achieve the blackbox behavior I want. Furthermore (maybe related?): the above describes the behavior after setting

model blackbox on

, when I set

model blackbox off

the behavior is the same except that

model *cell_name*

returns "module" which does not appear to be a valid model type according to the documentation. Nor is that difference of behavior documented in the section on model blackbox on|off in the documentation at http://opencircuitdesign.com/netgen/ maybe I'm looking in the wrong place?

Hello everyone, I start to experiment with SRAM memories given by sky130A PDK, when i harden the "sky130_sram_1kbyte_1rw1r_8x1024_8.v" with an interface to work as a FIFO i had some LVS errors. Those errors are strange due to there aren't "vssd1_uq0" and "vccd1_uq0" in the design but those signals apears in the LVS report as (no matching pin). Attach verilog files, config.file, and LVS log reports. Thanks in advance.