Hello everyone, I'm having a weird problem with lv...
# lvs
s
Hello everyone, I'm having a weird problem with lvs. I'm using a spice file extracted from magic and doing an lvs check against a spice file from my schematic. My extraction settings are ext2spice lvs, ext2spice merge conservative. Netgen can't see the devices in the magic generated spice file, it finds zero device instances. It doesn't work with other extraction settings either. It worked just fine a few weeks ago on simpler designs. Has anyone else run into this? Any comments would be much appreciated. I have attached the two files and the terminal output in the comp file.
m
1. When you netlist, be sure to select
Simulation -> LVS netlist: Top cell is a .subckt
2. You don’t have any pins on your layout. Add pins that correspond to your schematic. 3. When you run netgen, what command do you use?
s
1. I now have the option enabled. 2. I have labels on my nodes. Are "pins" the port option in magic where i can set labels as ports? I thought that was for digital designs. I have tried ports and there is no difference. 3. netgen -batch lvs mirrors.spice mirrors_lvs.spice /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
m
1. Could you post your new
mirrors_lvs.spice
? 2. See https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1662740537585699 3. You probably want something like
netgen -batch lvs "mirrors.spice mirrors" "mirrors_lvs.spice mirrors_lvs" /usr/local/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
if your subckt names are different.
s
I'm gonna try both solutions. The new spice netlist from xschem just lacks the comment out for line ".subckt mirrors_lvs". I will also try adding i/o pins to the schematic instead of lab_pins, even though this is just a small block of a circuit.
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