Hello, I am getting LVS errors on step#34 with mismatched vccd1 nets (34-user_project_wrapper.lef.log). I have a synthesized macro (from digital_unison.v) that I instance six times inside the user_project_wrapper.v with a generate block. In my user_project_wrapper config.tcl I provide PDN hooks for each genblk1 macro (formatted as described in https://open-source-silicon.slack.com/archives/C01DZSS46HL/p1662949330672169?thread_ts=1662946833.926449&cid=C01DZSS46HL):

### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
	genblk1\[0\].digital_unison_instance vccd1 vssd1 vccd1 vssd1, \
	genblk1\[1\].digital_unison_instance vccd1 vssd1 vccd1 vssd1, \
	genblk1\[2\].digital_unison_instance vccd1 vssd1 vccd1 vssd1, \
	genblk1\[3\].digital_unison_instance vccd1 vssd1 vccd1 vssd1, \
	genblk1\[4\].digital_unison_instance vccd1 vssd1 vccd1 vssd1, \
	genblk1\[5\].digital_unison_instance vccd1 vssd1 vccd1 vssd1 "

I have also tried

set ::env(TAP_DECAP_INSERTION) 1

following https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1662949908087539 But the error remains:

NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper            

---------------------------------------------------------------------------------------
Net: genblk1\[1\].digital_unison_instance/ |Net: vccd1                                 
  digital_unison/vccd1 = 1                 |  digital_unison/vccd1 = 6                 
                                           |                                           
Net: genblk1\[4\].digital_unison_instance/ |(no matching net)                          
  digital_unison/vccd1 = 1                 |                                           
                                           |                                           
Net: genblk1\[0\].digital_unison_instance/ |(no matching net)                          
  digital_unison/vccd1 = 1                 |                                           
                                           |                                           
Net: genblk1\[3\].digital_unison_instance/ |(no matching net)                          
  digital_unison/vccd1 = 1                 |                                           
                                           |                                           
Net: genblk1\[2\].digital_unison_instance/ |(no matching net)                          
  digital_unison/vccd1 = 1                 |                                           
                                           |                                           
Net: genblk1\[5\].digital_unison_instance/ |(no matching net)                          
  digital_unison/vccd1 = 1                 |                                           
---------------------------------------------------------------------------------------
Netlists do not match.

Any suggestions on what else to try would be appreciated! @Mitch Bailey

Just a shot in the dark here, but maybe the

\[

is causing problems. Instead of

""

, you could try

{}

which is tcl for no substitution. You might also try increasing the

\[

to

\\\[

. Or getting changing the verilog to something like

_1_

. Check your logs for the message

Connecting $instance_name to $power and $ground nets.

where the variables have been replaced with actual values.

Yep! 7-pdn.log shows:

[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[0\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[0\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[1\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[1\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[2\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[2\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[3\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[3\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[4\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[4\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vccd1 of instance genblk1\[5\].digital_unison_instance is not connected to any net.
[WARNING PDN-0189] Supply pin vssd1 of instance genblk1\[5\].digital_unison_instance is not connected to any net.

I tried the braces and the extra escape characters...no luck...maybe I should just manually instance the macros and use normal names!

With braces, you may have to remove the backslashes altogether.

Ah...took out the escapes...issue persist. Going to try getting rid of the generate block next, thanks for the ideas!

Sorry about any confusion. The braces and extra escapes are mutually exclusive. You don't want to do both.

I had difficulties utilizing macros inside modules and got errors in LVS stage I see some projects in MPWs had achieved this kind of usage, but I had errors especially about power connections finally I harden all the macros separately and in the top module (user_project_wrapper) I only connected them and used no standard logic. I analyzed most of the MPW projects and figured that they also follow this approach. I can say from my experiences this way is easier to finalize the design, but dont take it for granted of course

Is the macro placement working? Not sure if the

FP_PDN_MACRO_HOOKS

is used before or after placement, but if the placement isn't correct, then I doubt that the power routing would work either. Here's an example https://open-source-silicon.slack.com/archives/C016G7Z8GDR/p1654756356715519?thread_ts=1654721694.939769&cid=C016G7Z8GDR

Good point! Some of my macro locations were bad, fixed, but the vccd1 error persists. Pulling up the mag layout it looks like vccd1 is connecting to some macros but not the others. Looking for typos in my files...

I seem to remember something about a minimum height for macros (maybe 250?). If the macros are shorter than the power grid, they might not get connected. You might be able to fix this by careful placement (ie. place them where you know vccd1 and vssd1 are.).

I had problems for 150um

Oh I see...excellent observations guys! The default FP_PDN_VPITCH seems to be 180 (setup in default_wrapper_cfgs.tcl) Will play around with the macro placement and PDN config params!

Although it may be possible to change the pitch of the power grid, be aware that for caravel/caravan integration, there is an XOR check to ensure that the interface between the

user_project_wrapper

and

caravel

has not been changed. This may includes the power ring and the power grid connections.

I was able to move just the macro placement and now LVS on vccd1 is good! Thanks a ton for the excellent suggestion!!