hi everyone. This seems to be a very weird issue to me. Why is the tool complaining regarding these pins in user_project_wrapper?

@Asma Mohsin Can you share your rtl for

user_project_wrapper

and your

config.json

file? Often the power pins are enclosed in an

ifdef

in the verilog. If the config file does not have this line

"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",

the pins may be ignored.

config (1).json,user_project_wrapper.v

@Asma Mohsin the

summer_school_top_wrapper

has power pins that are commented out.

summer_school_top_wrapper FPGA_IGNITE ( 
   /* `ifdef USE_POWER_PINS
	.vccd1(vccd1),	// User area 1 1.8V power
	.vssd1(vssd1),	// User area 1 digital ground
     `endif
    */

This might be (part of) the problem.

this is not an IP. plus i enabled them initially but was getting linter error that no such pins found

@Asma Mohsin I’m not sure whether or not this is an ip has any significance. When performing the power connections, there should be power pins in not only the instantiations but also the module definitions. Do the module definitions contain power pins?

Hi @Asma Mohsin were you intending to do a paid chipIgnite submission of your chip for the November 2024 shuttle?

@Mitch Bailey I originally declared them in module instantiation but was getting linter erros on these pins so I commented them out. But you are right. I just turned liner off now, instantiated these pins everywhere back, and didnt get this error. Thankyou