Sorry, @Asma Mohsin let me clarify... I recall that newer versions of Yosys (?) that are part of the flow now synthesize

$display

statements to

$print

and these are not real cells. If that's what's happening to you, I'm not sure why, but the workaround seems to be commenting out any Verilog

$display

statement or otherwise eliminating it from evaluation by wrapping it in an ``ifdef` that is never defined -- Let me know whether this helps or not :)