Does the caravels architecture support floating point.

I can't find what configuration of the VexRiscv core is used in the management SoC https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/ https://caravel-harness.readthedocs.io/en/latest/description.html

Also the architecture block diagram says nothing about a FPU in its diagram.

previously I guess it used picorv32 which doesn't have a floating-point configuration available so I expect the vexriscv version doesn't have an FPU either, but you can still use soft float

I expect the Caravel RISC-V to be very minimal and not even support multiplication, it's meant as an interface between pads and internal of user_project for debug purpose: implementing more extensions than RV32I (32 registers) or RV32E (16 registers) base integer instruction set on a default peripherical would just reduce the room for the user area with little benefits. It would be good that eFabless documents clearly the implemented instruction set in their doc