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hi, I am getting this hold violation at step 31 us...
# chipignite
s
hi, I am getting this hold violation at step 31 using openlane for a very simple example code.I added a always block in the part with error but still the error is not solved and I am little stuck as errors are not very clear. this error i get after running make user_project_wrapper . make user_proj_example is clean https://github.com/Samarthjainabout/openlane_cadence_verification/tree/main/openlane_holdviolations
v
attaching logs will be useful to debug
s
the signoff.zip folder in git is thelog?
https://drive.google.com/drive/folders/1sQcUG4BMgFUFlkNMkD6bsPPP59nztV9w?usp=sharing I have uploaded the entire run folder as I wasn't sure which log to provide.
m
@samarth jain The 
config_in.tcl
file has 
set ::env(SYNTH_ELABORATE_ONLY) "1"
. This means that the 
user_proj_example
macro will be placed and routed without any consideration of timing. There will be no buffers inserted to alleviate fanout, slew, or other timing errors. You might try flattening 
user_proj_example
in 
user_project_wrapper
with synthesis on the top level. I remember seeing a document detailing the steps, but can’t seem to find it at the moment. @Anton Maurovic (efabless support)?
s
does make user_project_wrapper command not do that? @Vijayan Krishnan
m
@samarth jain 
make user_project_wrapper
will create a 
user_project_wrapper
verilog gate level netlist and corresponding layout. Whether or not that includes hard macros or flattened soft macros is up to the settings in the 
config.json
file.
a
Hi @samarth jain, in our session tomorrow I think we need to make sure you are using our standard repo template with all source materials & output artefacts in the correct places, because this will make it much easier for us to review and provide support -- plus, this is now mostly a requirement to ensure our platform correctly accepts all data, including doing LVS checks.
I'm going to adjust our meeting to start 15mins earlier, and run for a total of 1hr.
Or instead of going through the repo structure tomorrow: If you are comfortable doing so, I strongly suggest you try to clone a clean copy of https://github.com/efabless/caravel_user_project and put your simple example code that you mentioned into the right places, namely: • verilog/rtl/ • openlane/ -- put your macro definitions and config in there • gds/ -- commit these files also. Run "make compress" before committing to ensure they are small.
I think you have mostly done this in your https://github.com/Samarthjainabout/openlane_cadence_verification/tree/main/openlane_holdviolations repo, but it lacks the proper "openlane" and "gds" subdirectories, and it looks like it mixes some openlane "run" content in at the root level with your actual project.
j
Hey, I'm also facing the same issue, did you get yours resolved?
s
Hi Yes, I added sequential logic to la pins to add delay and for any place where data is driven by it, I will put a if statement with La pin inside condition.
j
Can you give an example on how you did this?
s
Copy code
`default_nettype none

module user_proj_example (
`ifdef USE_POWER_PINS
    inout wire vccd1,    // User area 1 1.8V supply
    inout wire vssd1,    // User area 1 digital ground
`endif

    // Wishbone clock input
    input wire wb_clk_i,
    input wire wb_rst_i,     // External reset signal

    // Logic Analyzer Signals
    input wire la_data_in,    // Single bit input
    output wire [127:0] la_data_out,  // 128-bit output, but we only drive the first 2 bits
    input wire [127:0] la_oenb  // Enable signals from logic analyzer
);

    // Declare internal signal for controlled clock and reset
    wire controlled_la_data_in;
    wire rst;
     wire clk;
    wire la_write;  // Single-bit la_write
     wire valid;     // Additional valid signal to control logic

    // Use logic analyzer enable signal to control reset and data flow
    // If LA probe [65] is enabled, control the reset with the logic analyzer signal
    
    // Define the valid signal based on some condition (you can adjust this as needed)
    assign valid = (wb_rst_i == 1'b0);  // In this case, valid when reset is not active, adjust as needed
    
    assign rst = (~la_oenb[65]) ? la_data_in : wb_rst_i;
    assign clk = wb_clk_i;
    // If LA probe [0] is enabled, control the input data from LA, otherwise it's high impedance
    assign controlled_la_data_in = la_oenb[0] ? la_data_in : 1'bz;
  // Derive single-bit la_write signal from la_oenb and valid signal
    assign la_write = ~la_oenb[63] & valid;  // Single-bit la_write logic with valid condition


    // Instantiate the tiny_test module with controlled reset
    tiny_test counter(
        .clk(clk),        // Use wb_clk_i as the clock signal
        .rst(rst),             // Reset signal controlled by LA or wb_rst_i
        .d(controlled_la_data_in),  // Input data is now controlled by LA signal
        .q(la_data_out[0]),    // Output q
        .qb(la_data_out[1]),    // Output qb
        .la_write(la_write)      // Single-bit la_write controls data updates
    );

    // Set remaining bits of la_data_out to high impedance to avoid shorts
    assign la_data_out[127:2] = {126{1'bz}};

endmodule

module tiny_test (
    input wire clk,
    input wire d,
    input wire rst,  // Reset signal (controlled by LA or external)
    output reg q,
    output reg qb,
    input wire la_write // Single-bit la_write controls when data is written
);

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            q <= 0;  // Reset q to 0
            qb <= 1;  // Reset qb to 1
        end
        else if (la_write) begin
            q <= d;      // Set q to the input d
            qb <= ~d;    // Set qb to the complement of d
        end
    end
endmodule

`default_nettype wire
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