@Sara N @jeffdi could you give us an updated estimate for die delivery for ChipIgnite 2211Q-R pls? status page shows as October, but I doubt I'll get them today! Thanks

Hello everyone, looking for some pre-tapeout LVS help. Our top level is

TOP_mixed

, which contains a

TOP_digital

and

TOP_analog

macro (hand wired together).

TOP_digital

was hardened seperately in Openlane then instantiated into

TOP_mixed

. Initially I forgot to inlude

TOP_digital.v

to the LVS config. It seemed to pass LVS but with this warning referring to TOP_digital being a black box:

So I then included

TOP_digital.v

(the gate level which Openlane had previously generated) and its caused it to fail, but I think its just because of a mismatch between bus/pin ordering somewhere in our verilog netlists? The user_project_wrapper comparison is complaining about mismatched pins, however all of these are present in both left and right columns, just in a different order. All the pins its unhappy about are all the ones we used in

TOP_digital

.

image.png

These are the verilog files we have given it (the Analog module is in spice, and Netgen is happy about that one):

Hi, Currently I can't push to efabless server:

git push -u ef-repo

# here I enter passphrese for the key

fatal: protocol error: bad line length character: Erro

2 days ago I was successfully pushing with the same commands and keys

Now it's working, maybe a local or remote connection problem

yes, I'm also having problems pushing and the web interface won't come up

getting me a 502 Bad Gateway error

looks like it's overloaded or something

now working again

Sorry if answered early but what is the latest time that we can submit for CI2311 ? Which time zone what time?

************************* As some of you are aware, we have been experiencing some performance issues with repositories on the efabless platform. To mitigate these issues, we have temporarily disabled mirroring between repos. Please reach out to us if this creates an issue for your submission. We will update you when this feature has been re-enabled. Thank you for your continued patience and support. *************************

Regarding Klayout FEOL and BEOL DRC violations on the pre-check, where is the best place to correct these? Directly in the user_project_wrapper.gds which Openlane generates, or in the .gds of the Macro we are feeding to Openlane to build (or does it not really matter?)

For analog designs i.e.

user_analog_project_wrapper.gds

I did these corrections on final gds opened inside klayout.

@Ellen Wood If you are absolutely never going to modify the original mag data, and are never going to run openlane again, you can modify the top level

gds/user_project_wrapper.gds

directly. However, if you run openlane again, you’ll need to make the same corrections. If possible, I recommend modifying the original mag data for analog designs. You’ll need to run all the parent openlane steps after creating the gds though.

Is there a full checklist specifically for analog projects somewhere?

If anybody has 30 minutes today to walk me through a couple things with the analog/mixed-signal toolchain then you might save me many hours and I'll be eternally in your debt!!

Hello, I have successfully merged my macro into user_project_wrapper. However, after the flow completed, I noticed my 2.syn_sta_summary setup violation. I think the real error in config.json is because I set it wrong or forgot to set a certain variable. Please help me.

************************** <!channel> The Efabless platform has just been updated for precheck and tapeout. Precheck and tapeout both support the openframe version of Caravel for those who are using that. There are also some bugs addressed in this version of precheck. The offline version of precheck has been updated to address some issues with LVS. **************************

How to update offline version of precheck ?

************************* Hello <!channel> We’ve had multiple requests for extending the deadline for the CI 2311 shuttle. We also rolled out an update to the precheck and tapeout flows over the weekend including support for Caravel Openframe. Due to these considerations - we have decided to make a one-time extension to the deadline for the CI 2311 shuttle to November 15 @ 23:59 pacific. *************************

When submitting to a shuttle, is the final submission step final (meaning the design cannot be updated)?

Hello Everyone, Join us on Nov. 16th at 9 AM PT for an insightful webinar! 🗓️ Explore the latest ASIC developments with Jeff DiCorpo and Matt Venn, including OpenFrame - a new Caravel version that expands your design possibilities by 50%. https://efabless.zoom.us/webinar/register/9416986830000/WN_HMIoqYriRH6uW4ci2CCRIQ

Hello <!channel> This is a reminder that the deadline for the CI 2311 shuttle is today, November 15 @ 23:59 PT.

Hi, can someone tell us what happened to the bare dies from chipignite run 2211Q? We specifically asked for them, which was confirmed by @jeffdi to be 50 QFNs + 50 bares for each caravel, because we need to do on die probing, but we received all 100 QFNs!

For wedge bonding on the bare die pads, is there a maximum number of grams-force that should be used? We've been dealing with some shorts when wedge-bonding our parts without about 27 g... they seem to mostly be on the HV_clamped pads

Is this the real status of the number of reserved slots? It's always zero