hi all, I was wondering if there is documentation ...
# chipignite
e
hi all, I was wondering if there is documentation for how the precheck, tapeout jobs work/where they look for files? The video seemed to just instruct users to click "Submit"- I am not planning on using the caravel chipframe/repo so I'm a little unclear what's expected in terms of collateral
a
Hi @Elam H Day-Friedland, the source code and some documentation for the MPW Precheck can be found in its repo. There is not much documentation on the Tapeout job, but I can quickly summarize what it does: 1. Integrates your conforming user project wrapper GDS into one of our 'frames' (Caravel, Caravan, or OpenFrame; i.e. the padring and SoC if applicable) 2. Runs "fills" (empty areas on all layers are pattern-filled to meet manufacturing requirements) 3. Does final DRC & especially MR ("Manufacturing Required") rule checks to ensure manufacturability. 4. Provides final combined GDS (including fills) for the full die.
Note that submissions for fabrication with Efabless must use one of Caravel, Caravan, or OpenFrame... or optionally now also "Caravel Mini" (per chipIgnite Mini). When you said you're not planning on using one of our templates, did you have something in mind that you were trying to accomplish instead?
e
I see, thanks! the repo looks like what I was using for- some of my peers previously said they could just upload a GDS to some portal as long as the IO cells were in the correct positions. is that still possible?
(we used proprietary decks for LVS+DRC)
a
The mandatory requirement is one of the following files:
Copy code
gds/user_project_wrapper.gds         # For Caravel.
gds/user_analog_project_wrapper.gds  # For Caravan.
gds/openframe_project_wrapper.gds    # For OpenFrame.
...preferably as a
.gds.gz
compressed file instead. That GDS represents your own user project area which must conform to our template, in order to overlay the respective (fixed) frame (padring and, in the case of Caravel & Caravan, SoC). So, you don't (and cannot) provide the padring and IO cells, though if you are ordering bare dice you have the option of including additional IO cells inside your user project area that are unrelated to our padring (which will still be there in the fabricated silicon).
Assuming you are connecting to our padring, this is done through pin/port definitions around the edges of our template.
This typically makes it easier for you: You don't need to implement the integration, fill, and final full-chip DRC yourself.
I'll just get you links to the templates of the user project area (often called the "UPW" or "user project wrapper", even
user_project_wrapper
specifically for Caravel) that will probably help with preparing a design. @Elam H Day-Friedland are you mostly interested in an analog/custom-layout, mixed-signal, or primarily-digital design?
Sorry about that @Elam H Day-Friedland, have a look in https://github.com/efabless/caravel/tree/main/gds: • user_project_wrapper_empty.gds.gz: Caravel wrapper that contains edge pins (IOs around north, east, and west, and connections to Caravel SoC south), and PDN • user_analog_project_wrapper_empty.gds.gz: Caravan wrapper with only edge pins (no PDN) • openframe_project_wrapper_empty.gds.gz: OpenFrame wrapper with only edge pins -- larger area, because OpenFrame lacks the Caravel SoC You might also benefit from equivalent files: • DEFs: https://github.com/efabless/caravel/tree/main/def • LEFs: https://github.com/efabless/caravel/tree/main/lef
Can you tell me more about the nature of the project/design you're working on? i.e. will you use the padring, and are you interested in QFN-packaged parts?