I ran the following design with openlane but the la data in [0] is not connected @Anton Maurovic (efabless support)

@samarth jain Can you share your gate level verilog netlist? That’s what’s used to create the layout. Is

la_data_in[0]

connected there? Maybe synthesis optimized it away.

@samarth jain from what I can tell, the

la_data_in[0]

pin you have in the bottom of your screenshot is the one that belongs to the user_project_wrapper, right? I notice

la_oenb[0]

is also not connected. Is this hardening result definitely made from

user_project_wrapper.v

as shown in your attached zip file? You should push your whole repo and make sure we have access to it

@samarth jain Thanks for sharing the repo. However, I wasn’t able to find the

verilog/gl/user_proj_example.v

file in the repo.

@Mitch Bailey its uploaded. https://github.com/Samarthjainabout/openlane_cadence_verification/tree/main/verilog/gl/gl

@samarth jain Looking at the gate level verilog

> grep la_data_in verilog/gl/gl/user_proj_example.v
    la_data_in,
 input [127:0] la_data_in;
 sky130_fd_sc_hd__dlygate4sd3_1 hold131 (.A(la_data_in[48]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold150 (.A(la_data_in[53]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold17 (.A(la_data_in[55]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold201 (.A(la_data_in[65]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold21 (.A(la_data_in[54]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold25 (.A(la_data_in[50]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold29 (.A(la_data_in[49]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold34 (.A(la_data_in[59]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold39 (.A(la_data_in[60]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold44 (.A(la_data_in[57]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold49 (.A(la_data_in[63]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(la_data_in[51]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold54 (.A(la_data_in[56]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold59 (.A(la_data_in[62]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold64 (.A(la_data_in[61]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold69 (.A(la_data_in[58]),
 sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(la_data_in[52]),
 sky130_fd_sc_hd__buf_2 input17 (.A(la_data_in[64]),

it appears that

la_data_in[0]

is not used - it has been optimized out. This can happen to inputs that do not effect any of the verilog outputs.

But I have defined it has input 😅 . How to make sure it is connected?

It’s not that it’s not defined as an input. It’s that the input does not effect the output. yosys apparently thinks that the value of or any change in

la_data_in[0]

will have no effect on any of the outputs and therefore it and any associated circuits are irrelevant.

@samarth jain can you share your RTL (before synthesis, i.e. not just GL) that depends on

la_data_in[0]

? It might be easy to explain why it has been optimized out, if we see the RTL -- To back up what Mitch is saying, yosys has found that your logic is not in any way affected by a change in

la_data_in[0]

which is why it is left disconnected. In a truth table, this signal would be an 'X' (don't care)

<https://github.com/Samarthjainabout/openlane_cadence_verification/tree/main/verilog/rtl>

has the rtl files

Diodes are typically inserted for antenna repair

Why only for clk signal? Should it be there for all la_data_in as well

@samarth jain I don't know, but from what I understand: whether an antenna violation exists and needs repair for any given wire depends on multiple factors... including total length and partial length, routing layers, and what's on each end (including the area of the gate that the wire is connected to). I think this makes it hard to predict, since: gate sizes may vary a lot depending on what OpenLane determines it needs for fixing hold/setup violations, and this can be different for each path and path placement in the overall routing; and routing may go up and down layers all over the place; and one end may naturally discharge more than that for other paths. The much shorter answer is: I don't know, but you should trust it.

ya i was not doing this, make user_proj_example

@samarth jain is your repository https://github.com/Samarthjainabout/openlane_cadence_verification? Is it up-to-date with the latest Verilog? If so, can you also share your

openlane/*/config.json

files?