open-source-silicon.dev

Is there a way to force wishbone reset <@U06H50VMDPU>  via firmware?

Hi <@U053UFMPKDW>, I assume you mean you must cause the wb_rst_i signal to become asserted for a brief period, because it must be asserted for your design in the user project area (rather than simply resetting the RISC-V CPU)? I don't know the answer, but be aware that if it were possible, this would also reset the RISC-V CPU itself. Is that OK?

I think you can do this to cause the SoC to pulse its own internal reset -- on a GF180 chip I'm testing, it at least resets -- but I don't think it actually pulses the `wb_rst_i` signal (<@U016EM8L91B> do you know?) despite what <https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/generated/ctrl.html#ctrl-reset|the documentation> implies:
```*(volatile uint32_t*)CSR_CTRL_RESET_ADDR = 1;```

<@U06H50VMDPU>:  The `reg_reset` register you cited has something to do with the processor's debug function.  It does not reset the wishbone.  The wishbone reset is connected to the digital reset;  you can theoretically do this from inside a program by setting the `reg_hkspi_reset` register to 1.  But that is not a self-resetting bit, so it will just raise reset and halt the processor, leaving reset applied.
It can be done from _outside_ the processor by setting (and clearing) the same reset bit through the housekeeping SPI.
The recommended way to have an independent reset for the user project is to set up a logic analyer bit as the user project reset signal.

Thanks <@U016EM8L91B>. So <@U053UFMPKDW>, an existing chip not already designed with a secondary/independent reset cannot self-assert its own `wb_rst_i` (unless you were to, say, design an external circuit that your firmware can trigger via GPIO to the external RESETb pin). For an upcoming chip design needing this capability, using an LA pin (as Tim suggested) would be a good idea.