Has anybody had the problem of DRC violations when trying to harden a macro into

user_analog_project_wrapper

, even though the macro itself passed the flow without DRC violations? I've tried moving the macro, rotating it, and even resizing it by running the macro flow again, but nothing has changed.

What are the DRC violations? This might be a problem with the analog macro having layout that collides with the power grid on the top metal layers. There are ways to tell openlane to avoid power routing over the block, if that is the case.