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Hi everybody, Im having an issue with a mixed sign...
# caravan
i
Hi everybody, Im having an issue with a mixed signal design on the caravan harness when i try to integrate an analog macro in to a digital one. The openlane flow make it trough the step 41 the LVS. But the netlist in 3 nets. on the "41-lvs.lef.log" file the only mismatch i found is this one
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Circuit 1 contains 983 devices, Circuit 2 contains 983 devices.
Circuit 1 contains 1005 nets,    Circuit 2 contains 1002 nets. *** MISMATCH ***
Anyone could give some hints of how to solve this?
m
@IVO GAY CARAMUTI It may be because your analog macro is not connected to power, but can’t be sure without the LVS report file. Can you share your 
config.json
file and the lvs report (file name should be right after the message you shared from the log file)?
i
Sure here are the files that you asked for.
41-signal_generator.lef.lvs.logconfig.json
m
If you’re not using openlane2, then you need to add a 
,
before the closing 
"
on the first line.
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"FP_PDN_MACRO_HOOKS": [
        "adc1 vccd1 vssd1 vccd1 vssd1,",
        "adc2 vccd1 vssd1 vccd1 vssd1"
    ],
👀 1
‼️ 1
Check the results of the pdn step for warnings.
i
It fails in the same step 41. In the PDN step im getting this warings
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[WARNING PDN-0189] Supply pin VDD of instance adc1 is not connected to any net.
[WARNING PDN-0189] Supply pin VSS of instance adc1 is not connected to any net.
[WARNING PDN-0189] Supply pin VDD of instance adc2 is not connected to any net.
[WARNING PDN-0189] Supply pin VSS of instance adc2 is not connected to any net.
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vccd1 is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[WARNING PSM-0030] VSRC location at (79.790um, 109.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 111.520um).
[WARNING PSM-0030] VSRC location at (919.790um, 109.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (943.440um, 111.520um).
[WARNING PSM-0030] VSRC location at (359.790um, 249.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (482.640um, 247.520um).
[WARNING PSM-0030] VSRC location at (79.790um, 529.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 530.400um).
[WARNING PSM-0030] VSRC location at (919.790um, 529.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (943.440um, 530.400um).
[WARNING PSM-0030] VSRC location at (359.790um, 669.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (482.640um, 671.840um).
[WARNING PSM-0030] VSRC location at (79.790um, 949.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 949.280um).
[WARNING PSM-0030] VSRC location at (919.790um, 949.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (943.440um, 949.280um).
[WARNING PSM-0030] VSRC location at (359.790um, 1089.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (329.040um, 1090.720um).
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net vssd1 is not explicitly set.
[WARNING PSM-0021] Using voltage 0.000V for ground network.
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[WARNING PSM-0030] VSRC location at (79.790um, 109.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (98.640um, 84.280um).
[WARNING PSM-0030] VSRC location at (919.790um, 109.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (866.640um, 108.800um).
[WARNING PSM-0030] VSRC location at (359.790um, 249.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (559.440um, 250.240um).
[WARNING PSM-0030] VSRC location at (639.790um, 389.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (713.040um, 391.680um).
[WARNING PSM-0030] VSRC location at (79.790um, 529.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (14.260um, 527.680um).
[WARNING PSM-0030] VSRC location at (919.790um, 529.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (866.640um, 527.680um).
[WARNING PSM-0030] VSRC location at (359.790um, 669.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (559.440um, 669.120um).
[WARNING PSM-0030] VSRC location at (639.790um, 809.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (713.040um, 810.560um).
[WARNING PSM-0030] VSRC location at (79.790um, 949.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (98.640um, 951.440um).
[WARNING PSM-0030] VSRC location at (919.790um, 949.760um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (866.640um, 952.000um).
m
The power pins on the 
adc
macro appear to be 
VDD
and 
VSS
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Net: adc1/VDD                              |Net: dummy_972                             
  adc_top/VDD = 1                          |  sky130_fd_sc_hd__conb_1/proxyHI = 1      
                                           |                                           
Net: adc2/VDD                              |Net: dummy_973                             
  adc_top/VDD = 1                          |  sky130_fd_sc_hd__conb_1/proxyHI = 1      
                                           |
So you’ll want to use
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"FP_PDN_MACRO_HOOKS": [
        "adc1 vccd1 vssd1 VDD VSS,",
        "adc2 vccd1 vssd1 VDD VSS"
    ],
@CELINA BOSSA same problem?
i
Do i need to add VDD and VSS to the "VDD_NETS" and "GND_NETS"
m
VDD
and 
VSS
do not exist at the level that you are synthesizing. They are macro ports. So no, do not add them to 
VDD_NETS
, 
GND_NETS
.
👍 1
c
Yes, I think I have the same problem in the definition of the FP_PDN_MACRO_HOOKS. I'm checking. I will keep checking your next ansewers. Thank you!
i
Now its failing on the step 7 durin the generation of the PDN. im getting this error its like the via betewwn the two metal layers is missing.
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[WARNING PDN-0110] No via inserted between met4 and met5 at (97.8400, 501.4400) - (99.4400, 502.5800) on vssd1
[WARNING PDN-0110] No via inserted between met4 and met5 at (251.4400, 501.4400) - (253.0400, 502.5800) on vssd1
[WARNING PDN-0110] No via inserted between met4 and met5 at (405.0400, 501.4400) - (406.6400, 502.5800) on vssd1
[WARNING PDN-0110] No via inserted between met4 and met5 at (97.8400, 951.4400) - (99.4400, 952.5800) on vssd1
[WARNING PDN-0110] No via inserted between met4 and met5 at (251.4400, 951.4400) - (253.0400, 952.5800) on vssd1
[WARNING PDN-0110] No via inserted between met4 and met5 at (405.0400, 951.4400) - (406.6400, 952.5800) on vssd1
m
Progress! I’m not sure if it’s needed, but I’d add
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"dir::../../verilog/gl/adc_top.v"
to 
VERILOG_FILES
(leave it in 
VERILOG_FILES_BLACKBOX
) and then I’d delete all the other files listed in 
VERILOG_FILES_BLACKBOX
. 
VERILOG_FILES_BLACKBOX
should only contain your hard macros, I think. The 
met5
messages are concerning. The top metal is defined as 
met4
. What is the top metal in the 
adc_top
macro?
c
I keep answering here (we were working together). About the 
met5
, the 
adc_top
macro pins are defined as 
met4
and 
met5
. I think the problem lies in the fact that the flow can't place the vias to connect 
met4
and 
met5
. On the other hand, the actual macro we want to place is 
adc_top.v.
 However, this module also has macros inside (reminding files defined in 
VERILOG_FILES_BLACKBOX
) that are instantiated in the 
"dir::../../verilog/gl/adc_top.v"
. I think we may also have a mistake in how we define this macro.
m
There are 2 ways to create hard macros with regards to powering. The most common is to route power over the macro. However, this has the disadvantage of limiting the number of routing layers. For example, if you had a 3 level hierarchy, the lowest level could route to metal3, the middle level to metal4 and the top level to metal5. The other method of power routing uses a power ring. Each macro can use all the metal routing layers because the only connections to the parent power are on a power ring that surrounds the macro. For a more detailed explanation, see here.
c
Thank you! We will check the document.
👍 1
Apparently, we are using the ring method. I understand that it's not necessary to add or change anything in the top-level 
config.json
. As explained in the document, we set 
"FP_PDN_CHECK_NODES": false
, and step 7 regarding PDN passes; however, we keep having problems with the LVS. I am attaching two photos where it can be seen that the power grid (the brown lines) touches the outermost power ring of the macro (pink lines), but the vias are never created, and the power is never connected. Additionally, the power grid never reaches the inner power ring.
m
First, to read the layer definitions into klayout, use 
File
-> 
Load Layer Properties
and then choose 
$PDK_ROOT/$PDK/libs.tech/klayout/tech/$PDK.lyp
. I do not see a power ring on the macro. Be sure that the macro itself is hardened with 
FP_PDN_CORE_RING
set to 
true
. You may need to adjust the LEF manually to expose the power ring to the higher level router.
c
The 
config.json
 of the macro has:
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"FP_PDN_CORE_RING": 1
"FP_PDN_CFG": "dir::pdn_cfg.tcl"
And we can see a box of 
VDD
 and 
VSS
 around the macro desing. Isn't that the power ring? About adjust the 
LEF
, isn't that definition already exposing the power ring?
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MACRO adc_top
  CLASS BLOCK ;
  FOREIGN adc_top ;
  ORIGIN 0.000 0.000 ;
  SIZE 423.000 BY 403.000 ;
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER met4 ;
        RECT -2.080 3.280 -0.480 399.280 ;
    END
[...]
 END VDD
  PIN VSS
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER met4 ;
        RECT -5.380 -0.020 -3.780 402.580 ;
    END
[...]
   END VSS
[...]
Finally, I don't get what I should pay attention to when reading the layer definitions in KLayout.
m
> And we can see a box of 
VDD
 and 
VSS
 around the macro desing. Isn’t that the power ring? Great! I didn’t see a power ring on the screen shot you shared. Could you share a screen shot of just the macro? > About adjust the 
LEF
, isn’t that definition already exposing the power ring? Does the macro LEF have met5 obstruction over the vertical met4 power rails on the right and left of the macro? If so, you probably want to reduce the met5 obstruction area to allow connections to met4. > Finally, I don’t get what I should pay attention to when reading the layer definitions in KLayout. The screen shot showed unnamed layers. Using a klayout layer file would make displaying only the relevant layers simpler.
i
Here are two screenshots of the macro the first is only showing met4 and met5 that are used as the power grids, and the second one is the complete macro containing all the layers. About the Obstruction in the met5 and met4 in the macro .lef, we found some obstructions
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LAYER met5 ;
        RECT 94.400 258.580 254.960 364.890 ;
        RECT 94.400 235.580 254.960 250.480 ;
        RECT 94.400 212.580 254.960 227.480 ;
        RECT 94.400 189.580 254.960 204.480 ;
        RECT 94.400 166.580 254.960 181.480 ;
        RECT 94.400 143.580 254.960 158.480 ;
        RECT 94.400 35.950 254.960 135.480 ;
        RECT 265.500 102.500 298.330 110.850 ;
        RECT 265.500 288.000 298.400 297.000 ;
        RECT 294.400 28.000 408.000 44.000 ;
        RECT 294.400 50.500 408.000 67.000 ;
Shall we remove some of this obstructions o reduce the positions of the obstruction RECT ?
m
From what I can see, it appears that everything is connected. Where are you seeing errors?
Sorry, would you like to talk now?
c
Nono, sorry, misclicked
👍 1
i
As @CELINA BOSSA said before the error occurs when connecting the hardened macro to a top level power grid. the VDD_NETS and the GND_NETS are not connecting each other
c
To summarize, the error we are encountering is:
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Circuit 1 contains 983 devices, Circuit 2 contains 983 devices.
Circuit 1 contains 1005 nets,    Circuit 2 contains 1002 nets. *** MISMATCH ***
Upon observing the GDS file, we deduce that the missing 4 nets are the connections between 
vccd1
with 
VDD
and 
vssd1
with 
VSS
. In the last photo I sent, it can be seen that 
vssd1
never connects with 
VSS
.
m
Ok. So the images @IVO GAY CARAMUTI sent are the 
adc_top
macro, right? Can you load the LEF into klayout to check that the vertical met4 on the left and right are exposed (have openings in met5)?
✅ 1
Another option is to check that the horizontal met5 at the top and bottom is not covered by met4 obstruction. @Marwan Abbas might be able to provide better advice.
i
We checked the LEF file. In blue, the obstructions for 
met4
and 
met5
are visible. The red/pink grids represent the power grids made of 
met4
(vertical) and 
met5
(horizontal), both visible from the top and bottom, as well as from the right and left.
m
That is as expected. What does the top level power grid with macro placed look like?
i
We finally solved the issue with the design not connecting to the analog hardened macro. @Mitch Bailey Thank you very much for helping us to solve this issue. I and @CELINA BOSSA Could solve the problem by following your recommendations and the ones on this page and this document. By the way, I would upload our 
config.json
in case other people faces the same problem.
config.json
m
Congratulations!
🙌 1
thanks 2
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