Caravel has them connected with a ‘caravel_power_routing’ cell which is missing from caravan. Also, none of the ‘gio_control_blocks appear to connected (all layers shown): Am I missing something?

For my design I'm using io_analog[10:0], and io_clamp_low[2:1], and io_clamp_high[2:1] Looking here I've found the pin correspondence to the packaged chips: https://github.com/efabless/caravel_user_project_analog/blob/main/verilog/rtl/user_analog_project_wrapper.v From the comments, this looks good: io_analog[10:0] <---> mprj_io[24:14] However, I believe there is a typo for the io_clamp_high/low routing (line 96): /* Additional power supply ESD clamps, one per analog pad. The * high side should be connected to a 3.3-5.5V power supply. * The low side should be connected to ground. * * clamp_high[2:0] <---> mprj_io[20:18] * clamp_low[2:0] <---> mprj_io[20:18] * */ @User I assume this is not actually the case. Do you know what are the connections supposed to be here? Thanks!

Semi-related: In my design returning from tapeout I'm passing my power (1.8v) and ground through two of the io_analog pads (in hindsight I should have used the user area power supplies, but I was trying to avoid powering on any of the management SoC - didn't realize these were separate). @User Do the clamps rely on any of the user area power pads (vddxx, vssxx, or vccx) being active? In the user project area I have the clamps connected to my own power rails as would be typical. I'm intending to leave the formal user area power undriven unless they are connected to the clamps behind the scenes (in this case I'll simply tie the user area power to my power rails).

Hi , i am trying to open the user_analog_project_wrapper file downloaded from caravan repo: But getting the below error - Any solution ? Thanks Cell user_analog_project_wrapper has technology "sky130A", but current technology is "sky130B" Use command "tech load" if you want to switch technologies, or use "cellname delete user_analog_project_wrapper" and "load user_analog_project_wrapper -force" to force the cell to load as technology sky130B

Hmmm I just forked the project and ran the precheck which fails with

{{STEP UPDATE}} Executing Check 6 of 13: XOR
XOR CHECK FILE NOT FOUND in /home/pepijn/code/asic/caravel_lvds/precheck_results/27_JUN_2022___14_31_39/logs/xor_check.total
{{XOR CHECK FAILED}} The GDS file has non-conforming geometries.

(and also the default readme but that's fine)

What's going on with the analog pins here? Trying to figure out what's going on with ESD.

Hi all, I am having trouble with the MPW precheck for the user_analog_project. This is the output of my log on efabless.com:

[08/02/22 18:27:37 PDT] FAILURE
1 Check(s) Failed: ['Consistency'] !!!






[08/02/22 18:27:37 PDT] FAILED
STDOUT: Loading Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: Open Source Shuttle MPW Precheck | Starting Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: {{Project Git Info}} Repository: <https://gitlab.com/carllb52/mixed-signal-reram-mpw7-2.git> | Branch: main | Commit: 0c57b1bcff189728d081673a6982bd2f3bd13f41
STDOUT: {{EXTRACTING FILES}} Extracting compressed files in: mixed_signal_circuits-jun13
STDOUT: {{Project Type Info}} analog
STDOUT: {{Project GDS Info}} user_analog_project_wrapper: 94b6ca623f863196471e194445b4875966ebd3c2
STDOUT: {{Tools Info}} KLayout: v0.27.10 | Magic: v8.3.315
STDOUT: {{PDKs Info}} PDK: sky130B | Open PDKs: 05af1d05227419f0955cd98610351f4680575b95 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
STDOUT: {{START}} Precheck Started, the full log 'precheck.log' will be located in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
STDOUT: {{STEP UPDATE}} Executing Check 1 of 13: License
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
STDOUT: SPDX COMPLIANCE SYMLINK FILE NOT FOUND in mixed_signal_circuits-jun13/openlane/Makefile
STDOUT: {{SPDX COMPLIANCE CHECK FAILED}} Found 55 non-compliant file(s) with the SPDX Standard.
STDOUT: SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['mixed_signal_circuits-jun13/Makefile', 'mixed_signal_circuits-jun13/docs/Makefile', 'mixed_signal_circuits-jun13/docs/environment.yml', 'mixed_signal_circuits-jun13/docs/source/conf.py', 'mixed_signal_circuits-jun13/docs/source/index.rst', 'mixed_signal_circuits-jun13/netgen/run_lvs_por.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_verilog.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_xschem.sh', 'mixed_signal_circuits-jun13/netgen/sky130B_setup.tcl', 'mixed_signal_circuits-jun13/verilog/dv/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por.c', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por_tb.v', 'mixed_signal_circuits-jun13/verilog/rtl/example_por.v', 'mixed_signal_circuits-jun13/verilog/rtl/uprj_analog_netlists.v']
STDOUT: For the full SPDX compliance report check: mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs/spdx_compliance_report.log
STDOUT: {{STEP UPDATE}} Executing Check 2 of 13: Makefile
STDOUT: {{MAKEFILE CHECK PASSED}} Makefile valid.
STDOUT: {{STEP UPDATE}} Executing Check 3 of 13: Default
STDOUT: {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
STDOUT: {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
STDOUT: {{STEP UPDATE}} Executing Check 4 of 13: Documentation
STDOUT: {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
STDOUT: {{STEP UPDATE}} Executing Check 5 of 13: Consistency
STDOUT: HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
STDOUT: COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
STDOUT: MODELING CHECK PASSED: Netlist caravan is structural.
STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].
STDOUT: PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
STDOUT: COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (6 instances).
STDOUT: MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
STDOUT: LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
STDOUT: {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
STDOUT: {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
STDOUT: {{STEP UPDATE}} Executing Check 6 of 13: XOR
STDOUT: {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/outputs/user_analog_project_wrapper.xor.gds
STDOUT: {{XOR CHECK PASSED}} The GDS file has no XOR violations.
STDOUT: {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
STDOUT: Found 0 violations
STDOUT: 0 DRC violations
STDOUT: {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
STDOUT: No DRC Violations found
STDOUT: {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
STDOUT: No DRC Violations found
STDOUT: {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
STDOUT: No DRC Violations found
STDOUT: {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
STDOUT: No DRC Violations found
STDOUT: {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{FAILURE}} 1 Check(s) Failed: ['Consistency'] !!!

I am stuck at:

STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].

I belive there is currently a issue on the caravel repo: https://github.com/efabless/caravel/issues/105 If Anyone has any suggestions that would be greatly appreciated.

@Steven Bos has left the channel

@Tim Edwards Hello Tim I have watched your presentation on Caravan. You mentioned the we only have 11 Pads dedicated for analog, right? So how about if I need more than 11 pads for analog, is it possible? Thanks

@Tim Edwards Hi Tim, Quick question: Can the vccd1 and vccd2 support 3.3V in particular the HV standard cells?

@Tim Edwards Hello Tim, Quick question, can we apply negative voltage to the analog pads?

Hello, we're doing analog IC layout and have a user_analog_project_wrapper.mag. What's the next step? Does "make run-precheck" run LVS and DRC?

@Tim Edwards Hi Tim, I have a crossbar array with certain structure. And my inputs to the array through the analog pads are reverse ramp signal (3V or less level and frequency <1MHz). 1. Can the analog pad takes a reverse ramp signal. 2. Is it possible to program the SoC to generate a such signal to the analog pads or I have to give it from outside (function generator)? 3. I have a 4-16 decoder built from HV standard library, can I send the four bits from the SoC (0 for bit 0, and 3.3V for bit 1)? Thanks!

Hi @Tim Edwards I was wondering why we have level shifter in the gpio between the “*oe_n*, out, and *in*”signals and decoder as in the attached diagram?

Where can I find the schematic for the caravan ESD protection circuits? I'll have to route some custom protection for my submissions. In short: I'm using the caravan analog IOs for power because I aim to cut the circuits off the die for later integration, and I fear that the cutting itself might damage the circuits. @Tim Edwards

On the caravan-specific pads, there is no ESD whatsoever, except that there are three clamps for power supplies that can be hooked up (optional, and not connected by default). All the pad connections are metal going straight through from the user project area directly to the pad, with no other connections.

Is there a possibility to execute an equivalent of make user_project_example or make user_project_wrapper onboard the caravan ? We have been trying to perform this however without success although there exists a symilink to a Makefile in openlane foler which redirects to caravel/openlane, where one can find respective folders user_analog_project_wrapper and user_project_wrapper. In fact we are looking for a method to instantiate a "not so small" digital macro onboard caravan where we would like to interconnect it with our analog counterpart. The digital macro uses booth LA and WB bus so weould be a little bit painfull to route it manually. @Tim Edwards

err.jpeg

Hi @Tim Edwards! I am trying to develop analog pads, and in order to do so, I'd like to analyze the analog pads from caravan (those placed from mprj_io[14] to mprj_io[24] in analog connections). Do you know where can I find those? Are they in the Open_pdks IO's folder? I've searched in the caravel_user_project_analog folder without success

Good afternoon, @Tim Edwards 🙂 hope you are doing well! Iv'e been looking for some standard in terms of the wide of a pad cell. Did you follow any standard for it? Or is there any limit for how wide can i make a pad cell?

I'm struggling to get

make verify-mprj_por

to run on the caravel_user_project_analog repository. This is the output of

make verify-mprj_por

docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
        -v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
        -e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -u : efabless/dv_setup:latest \
        sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -DEF_STYLE -I /home/aidenp/pdk/ \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:30: Include file libs.ref/verilog/sky130_fd_io/sky130_fd_io.v not found
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
7 error(s) during elaboration.
*** These modules were missing:
        sky130_fd_sc_hvl__lsbufhv2lv_1 referenced 2 times.
        sky130_fd_sc_hvl__schmittbuf_1 referenced 4 times.
***
make: *** [Makefile:51: mprj_por.vvp] Error 7
rm mprj_por.elf
make: *** [Makefile:61: verify-mprj_por] Error 2

This github issue has the same issue as me and provides a partial solution: https://github.com/efabless/caravel_user_project_analog/issues/29 but after I modify the makefile to export

PDK

I get another error:

docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
        -v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
        -e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel -e PDK=sky130A \
        -u : efabless/dv_setup:latest \
        sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/aidenp/pdk/sky130A \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:97: Include file mgmt_core_wrapper.v not found
vvp mprj_por.vvp

I've tried running

make install_mcw

and exporting

MCW_ROOT

to docker in the makefile, but that doesn't fix the issue. Does anybody know how to fix this or if there is another version of caravel_user_project_analog that would work?

Hello everyone. I'm trying to read the GDS of the caravan cell "sky130_ef_io__analog.gds" (located in sky130A/libs.ref/sky130_fd_io/gds) in Magic. However, when I open it, I get an error message and the layout doesn't load correctly. Does anybody know how to fix this?

Does anyone know, if there is a good documentation for these kinds of pins in the Caravan SoC? Since I do have a High Frequency Project That would be quite important to me to get some specs...

Hello everyone. I'm having a problem running a parasitic extraction of a layout with a huge amount of vias. Because of its complexity in terms of number of vias, the extraction takes a really long time to be generated. Also, i checked the CPU consumption of magic when performing this process and realized that it only uses 1 core. Does anyone know how to set magic in order to run all of its capabilities using more than 1 core? That would be a great help in my case due to the reduction of time when running parasitic extraction

@mmehari has left the channel

Hi! Recently downloaded Caravel Analog User Project and after installing it I tried opening the user_analog_wrapper.mag, but end up getting the following error:

Cell user_analog_project_wrapper has technology "$PDK", but current technology is "minimum"
Use command "tech load" if you want to switch technologies, or use
"cellname delete user_analog_project_wrapper" and "load user_analog_project_wrapper -force" to force the cell to load as technology minimum

I ran "export PDK_ROOT=/home/AIC/caravel_user_project_analog/PDK" before downloading the pdk using volare. Any tips?

@Tim Edwards @Mitch Bailey @mehdi have installed the caravel_user_project_analog following the steps mentioned in this repo - https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst#install-caravel. I have a design's gds already with me. How can I integrate that into the user_analog_project_wrapper.gds .

Hello everyone! After reading through the caravel docs I came across the section about required directory structure. I was wondering what is MAGLEF file? And how do you generate a MAGLEF file for an analog design in Magic? Thanks in adavnace!

@Tim Edwards Can the logic analyzer inputs la_data_in used for 3.3V input digital signals?

@gatecat thank you for pointing me this project!