Ted
04/11/2022, 11:52 PMJared Marchant
04/20/2022, 8:26 PMJared Marchant
04/20/2022, 8:30 PMRyan R
05/31/2022, 4:04 PMPepijn de Vos
06/27/2022, 2:34 PM{{STEP UPDATE}} Executing Check 6 of 13: XOR
XOR CHECK FILE NOT FOUND in /home/pepijn/code/asic/caravel_lvds/precheck_results/27_JUN_2022___14_31_39/logs/xor_check.total
{{XOR CHECK FAILED}} The GDS file has non-conforming geometries.
(and also the default readme but that's fine)Pepijn de Vos
06/28/2022, 2:14 PMCarl Brando
08/03/2022, 9:56 PM[08/02/22 18:27:37 PDT] FAILURE
1 Check(s) Failed: ['Consistency'] !!!
[08/02/22 18:27:37 PDT] FAILED
STDOUT: Loading Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: Open Source Shuttle MPW Precheck | Starting Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: {{Project Git Info}} Repository: <https://gitlab.com/carllb52/mixed-signal-reram-mpw7-2.git> | Branch: main | Commit: 0c57b1bcff189728d081673a6982bd2f3bd13f41
STDOUT: {{EXTRACTING FILES}} Extracting compressed files in: mixed_signal_circuits-jun13
STDOUT: {{Project Type Info}} analog
STDOUT: {{Project GDS Info}} user_analog_project_wrapper: 94b6ca623f863196471e194445b4875966ebd3c2
STDOUT: {{Tools Info}} KLayout: v0.27.10 | Magic: v8.3.315
STDOUT: {{PDKs Info}} PDK: sky130B | Open PDKs: 05af1d05227419f0955cd98610351f4680575b95 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
STDOUT: {{START}} Precheck Started, the full log 'precheck.log' will be located in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
STDOUT: {{STEP UPDATE}} Executing Check 1 of 13: License
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
STDOUT: SPDX COMPLIANCE SYMLINK FILE NOT FOUND in mixed_signal_circuits-jun13/openlane/Makefile
STDOUT: {{SPDX COMPLIANCE CHECK FAILED}} Found 55 non-compliant file(s) with the SPDX Standard.
STDOUT: SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['mixed_signal_circuits-jun13/Makefile', 'mixed_signal_circuits-jun13/docs/Makefile', 'mixed_signal_circuits-jun13/docs/environment.yml', 'mixed_signal_circuits-jun13/docs/source/conf.py', 'mixed_signal_circuits-jun13/docs/source/index.rst', 'mixed_signal_circuits-jun13/netgen/run_lvs_por.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_verilog.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_xschem.sh', 'mixed_signal_circuits-jun13/netgen/sky130B_setup.tcl', 'mixed_signal_circuits-jun13/verilog/dv/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por.c', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por_tb.v', 'mixed_signal_circuits-jun13/verilog/rtl/example_por.v', 'mixed_signal_circuits-jun13/verilog/rtl/uprj_analog_netlists.v']
STDOUT: For the full SPDX compliance report check: mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs/spdx_compliance_report.log
STDOUT: {{STEP UPDATE}} Executing Check 2 of 13: Makefile
STDOUT: {{MAKEFILE CHECK PASSED}} Makefile valid.
STDOUT: {{STEP UPDATE}} Executing Check 3 of 13: Default
STDOUT: {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
STDOUT: {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
STDOUT: {{STEP UPDATE}} Executing Check 4 of 13: Documentation
STDOUT: {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
STDOUT: {{STEP UPDATE}} Executing Check 5 of 13: Consistency
STDOUT: HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
STDOUT: COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
STDOUT: MODELING CHECK PASSED: Netlist caravan is structural.
STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].
STDOUT: PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
STDOUT: COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (6 instances).
STDOUT: MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
STDOUT: LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
STDOUT: {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
STDOUT: {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
STDOUT: {{STEP UPDATE}} Executing Check 6 of 13: XOR
STDOUT: {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/outputs/user_analog_project_wrapper.xor.gds
STDOUT: {{XOR CHECK PASSED}} The GDS file has no XOR violations.
STDOUT: {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
STDOUT: Found 0 violations
STDOUT: 0 DRC violations
STDOUT: {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
STDOUT: No DRC Violations found
STDOUT: {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
STDOUT: No DRC Violations found
STDOUT: {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
STDOUT: No DRC Violations found
STDOUT: {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
STDOUT: No DRC Violations found
STDOUT: {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{FAILURE}} 1 Check(s) Failed: ['Consistency'] !!!
I am stuck at:
STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].
I belive there is currently a issue on the caravel repo: https://github.com/efabless/caravel/issues/105
If Anyone has any suggestions that would be greatly appreciated.Steven Bos
08/20/2022, 5:54 PMAbdulaziz
08/23/2022, 2:31 PMAbdulaziz
08/25/2022, 3:34 PMAbdulaziz
09/05/2022, 12:16 AMZexi Liu
09/11/2022, 11:30 PMAbdulaziz
09/26/2022, 8:29 AMAbdulaziz
09/28/2022, 2:43 AMLeonardo Gomes
10/27/2022, 3:28 PMTim Edwards
10/27/2022, 5:22 PMKrzysztof Herman
11/03/2022, 12:27 AMKrzysztof Herman
11/03/2022, 12:27 AMJhon Pinto
11/24/2022, 9:59 PMJhon Pinto
11/29/2022, 8:22 PMAiden Petersen
02/16/2023, 10:34 PMmake verify-mprj_por
to run on the caravel_user_project_analog repository.
This is the output of make verify-mprj_por
docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
-v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
-e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
-e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel \
-u : efabless/dv_setup:latest \
sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -DEF_STYLE -I /home/aidenp/pdk/ \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../ -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:30: Include file libs.ref/verilog/sky130_fd_io/sky130_fd_io.v not found
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
7 error(s) during elaboration.
*** These modules were missing:
sky130_fd_sc_hvl__lsbufhv2lv_1 referenced 2 times.
sky130_fd_sc_hvl__schmittbuf_1 referenced 4 times.
***
make: *** [Makefile:51: mprj_por.vvp] Error 7
rm mprj_por.elf
make: *** [Makefile:61: verify-mprj_por] Error 2
This github issue has the same issue as me and provides a partial solution: https://github.com/efabless/caravel_user_project_analog/issues/29
but after I modify the makefile to export PDK
I get another error:
docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
-v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
-e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
-e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel -e PDK=sky130A \
-u : efabless/dv_setup:latest \
sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/aidenp/pdk/sky130A \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../ -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:97: Include file mgmt_core_wrapper.v not found
vvp mprj_por.vvp
I've tried running make install_mcw
and exporting MCW_ROOT
to docker in the makefile, but that doesn't fix the issue.
Does anybody know how to fix this or if there is another version of caravel_user_project_analog that would work?Jhon Pinto
02/18/2023, 2:47 PMEnno
02/25/2023, 10:55 AMJhon Pinto
03/14/2023, 5:13 PMmmehari
04/05/2023, 7:43 AMKristoffer
04/10/2023, 7:46 PMCell user_analog_project_wrapper has technology "$PDK", but current technology is "minimum"
Use command "tech load" if you want to switch technologies, or use
"cellname delete user_analog_project_wrapper" and "load user_analog_project_wrapper -force" to force the cell to load as technology minimum
I ran "export PDK_ROOT=/home/AIC/caravel_user_project_analog/PDK" before downloading the pdk using volare.
Any tips?Pranav Lulu
04/12/2023, 8:09 AMKristoffer
04/12/2023, 10:06 AMPranav Lulu
04/15/2023, 11:04 AMJosuah Demangeon
06/07/2023, 9:49 AM