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Hi.
I'm doing a demo board debug and would like to measure the on-board clock. `<https://github.com/efabless/caravel_board/tree/main/firmware/chipignite/demos>`
Can I monitor the on-board clock via the GPIOs [14:15] in the caravan? I think it is impossible because GPIO 14 to 24 have been replaced by analog.
Is there a method to monitor the onboard clock in the caravan?

That is an issue with the caravan chip, since it shares nearly all of the same circuits with caravel.  Any method would have to be indirect (generate a pulse in software, run from the RAM so that it does not depend on delays from SPI access, and then know the number of instructions in that cycle, which is complicated enough that you would probably have to get it from simulation).

Thank you. I'll have to code some test programming.

<@U016EM8L91B> <@U053PUBUBJN> I saw Verilog related to Caravan that can output the two clocks on GPIO[31:30], and hopefully this exists in the current Caravan SoC that gets taped out. Not sure if it predates the chips you're testing though, Yonguk. I'll see if I can find it in any case

Here we go: <https://github.com/efabless/caravel/blob/27cbe49c90ba5362ad52c9968dd98e035c30c74f/verilog/rtl/housekeeping_alt.v#L51-L60>

HKSPI configuration is done on the same "clock monitor" register (0x1B) but bits [4:3] instead of [2:1]: <https://github.com/efabless/caravel/blob/27cbe49c90ba5362ad52c9968dd98e035c30c74f/verilog/rtl/housekeeping_alt.v#L402>

<@U016EM8L91B> Given the date, I suspect this is indeed part of Caravan since sometime after May 2023. Do you know whether this is true or not?

<@U053PUBUBJN> what's the date/shuttle of the chips you're testing?

Another possible way to test this, based on Tim's suggestion of "indirect" methods, is to use the UART. Send a stream of 0xAA out via GPIO[6]. Measure the width of each serial bit, expecting it to be ~9600 baud from a stable 10MHz clock input. Varying the clock should give a proportional and relatively stable (?) scaling of that bit width.

Oh, in fact, isn't flash_clk just the SoC core clock divided by 4?

<@U06H50VMDPU>:  To respond to your observation above about the clock output on Caravan:  Yes, you are right, and I completely forgot that I had already dealt with that possibility.  My quick check on it when I first responded a week or so ago was to look in `housekeeping.v` and I failed to properly check `houskeeping_alt.v`, where I would have found the solution.  That is by far the most convenient test point.

onboard clock.jpg

<@U06H50VMDPU> Thanks you. The chip I'm testing is a CI2404 shuttle, so I tried checking the on-board clock (<https://github.com/efabless/caravel_board/tree/main/firmware/chipignite/demos>) via GPIO [30:31] as you said, but I was able to check the clock up to 30Mhz.
However, the clock is not perfect pulse shape , which is normal, right?

<@U053PUBUBJN>:  I expect some ringing due to the very awkward output path;  if you're reading the signal from a pin on the development board, then the path is going through the wirebond, chip pin, daughterboard, M.2 connector, and development board.  None of the traces through that path are either properly terminated or properly impedance-matched, and the ground return path is just as bad.

Thanks for the advice, that was an expected ringing.