Hello everybody, I'm trying to add my analog desing into my digital desing. I want to create a blackbox in verilog to latter add the analog design there. Does anybody know which files I should modify to pass the OpenLane flow ? I've already add a LEF file with the characteristics of the blackbox but I'm still having problems.

@CELINA BOSSA Just treat your analog macro like a regular hard macro. The sample

caravel_user_project

has a top

user_project_wrapper

which instantiates a

user_proj_example

hard macro. If you are using

caravel_user_project_analog

as a base, you probably want to copy

openlane/Makefile

from

caravel_user_project/openlane/Makefile

if it is not the same. I don’t think the analog base repo was not really setup to run synthesis.

I'm not sure if I made myself clear. I have a digital design written in Verilog that passes the OpenLane flow. Now, I need to add a module in Verilog that should be treated by OpenLane as a black box. After I complete the OpenLane flow, I will manually add my analog design inside that black box. What files do I need to add or modify to pass the OpenLane flow with the analog black box?

@CELINA BOSSA Looking at how

user_proj_example

is instantiated in

openlnae/user_project_wrapper/config.json

$ grep -C2 user_proj_example .caravel_user_project/openlane/user_project_wrapper/config.json
    "MAGIC_DEF_LABELS": 0,
    "VERILOG_FILES_BLACKBOX": [
        "dir::../../verilog/gl/user_proj_example.v"
    ],
    "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
    "EXTRA_LIBS": "dir::../../lib/user_proj_example.lib",
    "EXTRA_SPEFS": [
        "user_proj_example", 
        "dir::../../spef/multicorner/user_proj_example.min.spef", 
        "dir::../../spef/multicorner/user_proj_example.nom.spef", 
        "dir::../../spef/multicorner/user_proj_example.max.spef"
    ],
    "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",

So you’ll need a verilog stub to put in

VERILOG_FILES_BLACKBOX

to show yosys that the block exists and has connections but it will not be synthesized. You already have

EXTRA_LEFS

You’ll need the

EXTRA_GDS_FILES

to specify the GDS file that will be placed in the output. You could temporarily create one from your LEF file in klayout or maybe magic. For timing, you probably want the

EXTRA_SPEFS

specification eventually.

Ok, I get it know, thank you very much for your help !

Make sure that the standard cell rows around the macro are wide enough to intersect with the necessary power rails.

I think that the flow is never connecting the vccd and vssd with the analog macro. I open the gds and both, vccd and vssd, never reaches the VDD and VSS pins of the analog macro.

Can you share your

config.json

file? Do you have

FP_PDN_MACRO_HOOKS

set correctly?