@Tim Edwards @Matt Venn @Mitch Bailey in wishbone master connection, ths clk pin does it always transmit clk or there is a way to control it in firmware to enable or disable the signal? i am sharing that clk pin with my digital design in user area but it does not seem to respond

@samarth jain I can help with LVS and maybe some openlane configuration problems, but unfortunately, I don’t have any experience with simulation.

I believe

wb_clk_i

is always active in the user project area and as the Caravel CPU clock simultaneously, and cannot be disabled. Thus, if the Caravel CPU is able to run firmware, then it is because it is being clocked by

wb_clk_i

, and hence this signal should be permanently present in your user project area. Note that it is possible to disable that clock signal completely (in which case the CPU will also stop).

Anton is correect