Hi I cannot find any documentation on what layer 236:0 is for. Does anyone know its purpose?

Is OpenMPW stopped? 1. efabless.com homepage no longer have mentions of link to OpenMPW 2. No news regarding MPW-9 3. Status page has no info regarding mpw9 4. openmpw pages have a bunch of deadlinks

@mmehari has left the channel

Does anyone know if OpenLane is installed in the workstation provided by efabless for designing. Also how to install jupyter notebook or other packages since there is no network access.

hello everyone i need a help for my schematic design of 6T SRAM cell. for simulation how to initialize the value for Q Qbar in EDA tools (Sky130 efabless) . or can you please let me know how to simulate for read and write operation of a 6T SRAm in sky130. do you have any suggestion or any useful link to work on magic and xschem for sky130?

Can I get a RAM (32-bit wide 1K depth) in digital flow?

Would chipignite samples with wire bonding instead of WSCLP be feasable?

My design is intended for EM near-field experiments. For this purpose, a flip-chip / WSCLP is not suitable.

Hello, when is the next open submission for OpenMPW?

Hi all, We have received the MPW-3 parts. I have two questions regarding this: 1. There are ten breakout boards delivered but only two of them are marked as verified/pass. What does that mean? 2. How to understand which job ID refers to which project (if there are more than one submissions)?

RISC-V Day in Japan. https://riscv.or.jp/risc-v-day-tokyo-2023-summer/presenter-bios#MKE

Hello Efabless, Can a conference be arranged? We have been working since last couple of years on efabless-openlane-openrad-sky130. We have invented many new ways to work around the issues we faced. Varifying rtl, synthesis, timing placing the maceros. A lot of new ways of working we have used. These are valuable for all of us. We want to publish those in the form of papers. It would good to have conference in colaboration with IEEE or equivallent and indexed with explore or scopus or equivallent. I think efabless people are not so busy now, and they can organize a conference. And please make an option to present paper online. Please keep the online author registration mode under $100. We Indians can not afford to pay more for. Our salary in not much. Thanks in advance.

@Kennedy Caisley has left the channel

Excited to start testing! Request to Efabless. Please extend the Caravel datasheet tables to include more than just the Maximum Ratings (https://caravel-harness.readthedocs.io/en/latest/maximum-ratings.html). There should be sections for both Recommended Operating Conditions and Electrical Characteristics. Two versions are needed, one for SkyWater and another for Global Foundries. The following should be covered: • Which I/O primitives were implemented? • Are the inputs LVCMOS/TTL or CMOS threshold levels (+1.4V or 70%*VDD)? • Are the inputs Schmitt trigger, bus keeper or simple buffers? • What is the slowest allowable input slew rate (to avoid oscillation)? • Output drive characteristics The GF180 PDK is specified at both +3.3V and +5V. Are there any constraints for running the GF Caravel MPW0 at either I/O voltage? If the answers have already been posted, please indicate link. Thank you. :)

Is Efabless git down? getting time outs when trying to access https://repositories.efabless.com/

We are happy to share our Advanced Compact MOSFET (ACM) model for the Open-source IC design community. The ACM model has only 5-DC-parameters. The IC designers can use it in open-source or commercial circuit simulators due to the universality of the Verilog-A language. The IC community is free to reach out to us through the issues page at https://github.com/ACMmodel/MOSFET_model or our email acmmodelgit@gmail.com

Hai all, Herewith I have attached the screenshots of LUT4AB tile running flow and .JSON which is used for eFPGA. Kindly suggest your ideas with me to rectify setup violation. Advance thanks.

Hai all, Is there any public template for creating a repo (other than a Caravel project template) in eFabless? If yes, kindly share with me the details. Advance thanks.

[2:14 PM] Dear all, Good noon, I am facing LVS issues with BRAM using OpenLane. Herewith, I have attached the tiles for your kind reference. Kindly share with me your ideas to clear the same.

Hai all, For our design, I am facing an issue in the xor check using Open Lane. Kindly share with me your ideas. Herewith, I have attached the file for your kind reference. Advance thanks.

Hello, yesterday I tried to get the log data with the "Request Job Data" button on the efabless platform, but I didnt get the email after several attempts. What could it be that I'm doing wrongly?

@Mitch Bailey @Tim Edwards @Matt Venn @mkk I wanted to incorporate sram in my chip design, but as per document it has little info and asks to contact efabless regarding it.As the current caraval also dont have SPI, how can we increase on chip sram size?

@Tim Edwards @Matt Venn Hi, I needed some resistors for analog applications but the skywater page ( pfa) says this resistor is not suitable for it. Which resistors can I use for analog biasing? I need some 30 ohms resistors or near by

Hello @Tim Edwards @jeffdi @Mitch Bailey and anyone else who could help, together with @Mario Romero and @Alfonso Cortés we are trying to achieve tapeout wth the latest version of our design. However, our tapeout job fails, but we can't find the error on the logs. The project is the following, the efabless team has access to it: https://repositories.efabless.com/ac3e_chile_chipathon_team/AC3E_Open3LFCC_V2_repo We would really appreciate your help!

efabless staff has joined this channel by invitation from open-source-silicon.dev.

Hello @Tim Edwards @Mitch Bailey @jeffdi do you know who can help usunderstanding an error related to oeb in the platform precheck?

Hi all - I am running precheck on an openframe user project. And we are done to

[CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['Consistency', 'Klayout Metal Minimum Clear Area Density'] !!! Is it correct understud that Efabless will apply metal fill as part to the tape out process to Skywatar and that will take care of the Metal Minimum Clear Area Density error.

Can somebody provide a working testbench for gfmpw-1c? The directory verilog/dv is empty and using io_ports, la_test1, la_test2 or wb_port from main doesn't work.

Hi - Anyone know where to find the pinout/bonding diagram for chipignite 56 pin qfn?