@Tim Edwards @Anton Maurovic (efabless support) what is the minimum pulse width la in caraval can detect? I am not able to detect any La data out from user to management area signals. How long should I hold the signal

The Caravel CPU can only sample the LA pins at moments in time, by doing a read of the pin logic level in firmware. The CPU cannot see pin events (rising or falling edges) that occur between LA reads; it is not edge-sensitive, and doesn't have logic for reacting to changes in the pin state. Thus, the minimum pulse depends on how quickly the firmware executes (which is affected by the system clock, but also delays can be inserted for SPI reads from firmware). If you have a 10MHz CPU clock, I don't know how many cycles are required to do an LA read, but my guess is that the absolute minimum pulse you would detect is about 2 cycles (200nS), but more likely it would be more than that (maybe 4 cycles), and if there was an SPI read in between it would be substantially longer (at a guess, hundreds of cycles). It might be possible to simulate this, if you trace exactly what the CPU state is for each clock cycle (which I haven't tried to do).

A short routine copied to and executed out of SRAM would be the fastest way to detect a short signal.

SRAM? I don’t have SRAM ip in user area

@samarth jain: No, what I mean is that reading/writing to the logic analyzer is slow because it is gated by how fast the program is being read from the SPI flash chip, which is a dreadfully slow interface. You can copy part of a program into SRAM (or I guess it's probably DFFRAM, to be more specific) and then change the program counter register from the SPI flash to the RAM and run the code from there. That would be able to read the logic analyzer at the maximum rate of one sample per two clocks (maybe one? The VexRISC is pipelined. . .). In the Caravel design verification there is a testbench that does that, that you can use as an example. It depends on how fast you need to catch the signals on the logic analyzer, though. But even if the signals are relatively slow, the rate of the VexRISC reading from the SPI flash is not constant, making it very hard to get accurate timing through the logic analyzer.