There was a Stanford project on one of the early C...
# efabless
t
There was a Stanford project on one of the early ChipIgnite runs that was using a 2 GHz transfer, although I don't remember if that was input, output, or both. 2 GHz is impossible on the GPIOs. It should be able to be achieved on the caravan bare pads, since they are not capacitively loaded.
s
Is this pad part ok to use if I add it to caraval? @Tim Edwards . Can u share me the pad part name to be added in my gds which don’t have diodes etc so I can hook up high speed signals
t
That pad would work. Are you planning to do your own wirebonding or use probes?
s
I am doing flip chip . Thanks I will continue to use these pads
t
The empty space underneath on metal 4 is mainly for avoiding problems with wirebonding. For a flip-chip solution, you can probably get by with something simpler with just metal 5 and passivation opening. You shouldn't need the metal 4 ring around the edge, or have to keep out of the metal 4 region underneath the pad.
s
@Tim Edwards is there a part as u describe which I can use from pdk? no ring in metal 4 and just metal 5 with oxide open. or i just delete metal 4 ring and make it via to metal 5?
t
Just copy the cell and delete the metal 4 ring.
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s
Thanks, will do
@Tim Edwards ok solder bumps r possible. I will try ur suggestion to remove metal 4 ring in next tapeout and also try
@David Lindley in this pad gds which layer indicates the oxide needs to be removed? If I just put metal 5 will foundry remove top oxide for it by default or I need to insert some layer? I need no passivation on these pads
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d
@samarth jain pad.dg is the glass opening. Layer 76/20. Put that where you want bare metal.
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s
@David Lindley I have placed the Met5 and PAD drawing overlapping with 0.27 enclosure as shown in the snap shot below. But after the drc run i see some violations on these COuld you please suggest on solution or can it be waived
d
We don't check either of those pad rules. You should be good.