Hi how do i do my own design on openlane 1?

There are two parts of it. • The Verilog file(s) • The configuration files See the example SPM. Follow that. You have to write your own verilog file(s) and keep it where smp.v is kept. Keep the configuration files where spm config files are kept. Rune like spm is run. Creating analog design is difficult. There is no flow in the world which takes spice netlist to GDS. Take simple digital designs like UART, SPI, I2C, VGA. These are very well handled by OpenLane.