module demo1(input a, input b, output x); always @(a,b) begin x<= a&b; end endmodule

in the config.json define correct `CLOCK_PORT`name, if you don't have clock port make it empty

You mean edit tge file right

yes

The default config file assumes it is a sequential process right

your top module don't have port name

clk

but config.json has

Oh i never knew will try and see

The design is tiny, so the default PDN size options cannot make a connection to your circuit. The inverter design is pretty similar to what you're doing (tiny, clockless design) so use its configuration file as a reference: https://github.com/efabless/openlane-ci-designs/blob/main/inverter/config.json

How can i judge the size of the pdn i need?

For tiny designs, the default option just won't work. Your design is quite literally an and gate. The logs reported that the pitch of the PDN is too small, as shown in your screenshot. For a primer on power distribution networks, see here: https://openlane2.readthedocs.io/en/latest/usage/pdn.html For larger designs, you usually don't need to touch the PDN options, unless you're running into routing congestion issues in which case it may be prudent to increase the pitch between the sets of straps.

Is there a way to let the pdn scale automatically as per the circuit?