Hello, I have an issue I don't understand. My goal...
# openlane
c
Hello, I have an issue I don't understand. My goal is to connect the macros to the power. I defined the names of the power (VDD_core) and ground (VSS) in the config file. The power and ground are defined in the macro LEF file, and finally, in the Verilog, they are connected as follows:
.VDD (VDD_core), .VSS (VSS), ...
The error I encountered says I have a problem with
fp_pdn_macro_hooks
, but I have filled out this part. I don't understand what the issue is. If someone can help me, I would appreciate it. Thanks.
m
Hi @Charly Meyer, I’m not sure if its a problem with the
config.tcl
configuration scripts, but the
config.json
requires that the
FP_PDN_MACRO_HOOKS
have 5 parameters and then a
,
. Does this work (I added a
,
before the
"
)?
Copy code
set ::env(FP_PDN_MACRO_HOOKS) { "interface_low_instance VDD_core VSS VDD VSS,", \
"level_H2L VDD_core VSS Vdd_core VSS" }
c
In adding a comma before and after " , I have this error.
m
Can you share the
config.tcl
file?
c
sure, but it is a little bit the mess inside, I tried many things
m
Here’s a sample from a working config.tcl file. Looks like the
"
are not needed.
Copy code
caravel/signoff/mgmt_protect/openlane-signoff/config.tcl:set ::env(FP_PDN_MACRO_HOOKS) { mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1,  mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2,  powergood_check vccd vssd vccd vssd,  powergood_check vdda1 vssa1 vdda1 vssa1,  powergood_check vdda2 vssa2 vdda2 vssa2}
c
Yes, this syntax works, but I have another issue. I'll show you.
m
Looks like there’s a difference between openlane and openlane2 configuration variables. Are you using openlane or openlane2?