Hi , facing issue in LVS for 1t1r array created . For the transistor i have used 7 fingers. From the magic extracted layout , seems since device is extracting 7 different NMOS. And for schematic , single NMOS. Can you please suggest ? Command : netgen -batch lvs "xschem.spice 1T1R_16x16_W7u_xschem_RRAM_DEVICE_1608" "magic_layout.spice x1T1R_16x16_W7_RRAM_W0p5_16_08_layout" pdks/sky130B/libs.tech/netgen/sky130B_setup.tcl Contents of circuit 1: Circuit: '1T1R_16x16_W7u_xschem_RRAM_DEVICE_1608' Circuit 1T1R_16x16_W7u_xschem_RRAM_DEVICE_1608 contains 512 device instances. Class: sky130_fd_pr_reram__reram_cell instances: 256 Class: sky130_fd_pr__nfet_g5v0d10v5 instances: 256 Circuit contains 305 nets. Contents of circuit 2: Circuit: 'x1T1R_16x16_W7_RRAM_W0p5_16_08_layout' Circuit x1T1R_16x16_W7_RRAM_W0p5_16_08_layout contains 2048 device instances. Class: sky130_fd_pr__nfet_g5v0d10v5 instances: 1792 Class: sky130_fd_pr__reram_reram_cell instances: 256 Circuit contains 2081 nets, and 48 disconnected pins. Circuit 1 contains 512 devices, Circuit 2 contains 2048 devices. * MISMATCH * Circuit 1 contains 305 nets, Circuit 2 contains 2081 nets. * MISMATCH * Result: Netlists do not match. @Mitch Bailey @Tim Edwards

Magic will extract individual devices and does not recognize fingers. The LVS setup and netgen itself will handle the merging of individual devices in parallel. If it does not do a parallel merge, then it did not see the devices as being in parallel.

Thanks @Tim Edwards , i am not sure whether netgen does the merging , @Mitch Bailey - any idea if we need to enable any option

@Ryan R Your schematic has one device with

L=0.5 W=7 nf=7

. LVS does not consider the

nf

parameter. I believe the spice simulator will split this up into 7 parallel devices with

L=0.5 W=1

, but I may be mistaken. Your layout has 7 transistors in series which is not equivalent. You want to attach one source/drain of each transistor to one node and the other source/drain to a different node.

@Mitch Bailey - yes wanted to split the 7um to 1um each mosfets - which means they will be in series right ? . The same behaviour nf=7 should have, they should not split in parallel but in series right ??

In series, if

Wf=1

and

Lf=0.5

, they are roughly equivalent to

L=3.5 W=1

which does not match the schematic

L=0.5. W=7

. You want to connect all the

S

terminals to one node and all the

D

terminals to a different node.

@Mitch Bailey - i corrected , now seems the num devices are matching : But still LVS failing .

Getting closer! Your reram device names don't match. schematic

sky130_fd_pr_reram__reram_cell

vs layout

sky130_fd_pr__reram_reram_cell

sky130_fd_pr__nfet_g5v0d10v5 (256)         |sky130_fd_pr__nfet_g5v0d10v5 (1792->256)   
sky130_fd_pr_reram__reram_cell (256)       |(no matching element)                      
(no matching element)                      |sky130_fd_pr__reram_reram_cell (256)

Also, I suggest specifying the layout first to match openlane.

netgen -batch lvs "magic_layout.spice x1T1R_16x16_W7_RRAM_W0p5_16_08_layout" "xschem.spice 1T1R_16x16_W7u_xschem_RRAM_DEVICE_1608" pdks/sky130B/libs.tech/netgen/sky130B_setup.tcl

Currently, you have the schematic on the left and layout on the right. From

sky130B_setup.tcl

# NOTE:  In accordance with the LVS manager GUI, the schematic is
# always circuit2, so some items like property "par1" only need to
# be specified for circuit2.

@Tim Edwards What do you think the best way to fix the reram device name discrepancy? 1. Use an

equate

statement in the netgen setup file 2. Change the xschem primitive 3. Change magic extraction name

@Mitch Bailey modified - but still failing

Are you still running lvs using

schematic

first and

layout

second?

Also, I suggest specifying the layout first to match openlane.

Copy code

netgen -batch lvs "magic_layout.spice x1T1R_16x16_W7_RRAM_W0p5_16_08_layout" "xschem.spice 1T1R_16x16_W7u_xschem_RRAM_DEVICE_1608" pdks/sky130B/libs.tech/netgen/sky130B_setup.tcl

Check your extracted layout. This subckt has 4 terminals as expected.

.subckt x1T1R_W7_RRAM_W0p5_16_08_layout BL WL SL VSUBS
Xsky130_fd_pr__nfet_g5v0d10v5_Y5YTSN_0 SL m1_2626_224# WL WL SL WL WL m1_2626_224#
+ WL WL SL WL m1_2626_224# SL m1_2626_224# VSUBS sky130_fd_pr__nfet_g5v0d10v5_Y5YTSN
X0 BL m1_2626_224# sky130_fd_pr__reram_reram_cell area_ox=2.5e+11p
.ends

This subckt only has 1 terminal.

BL

,

WL

, and

SL

are not connected to the top level. Also, all the

SL

connections are to the same node (shorted).

.subckt x1T1R_1x16_W7_RRAM_W0p5_16_08_layout VSUBS
X1T1R_W7_RRAM_W0p5_16_08_layout_0[0] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[0]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[1] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[1]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[2] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[2]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[3] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[3]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[4] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[4]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[5] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[5]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[6] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[6]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[7] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[7]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[8] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[8]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[9] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[10] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[10]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[11] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[11]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[12] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[12]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[13] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[13]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[14] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[14]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
X1T1R_W7_RRAM_W0p5_16_08_layout_0[15] 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/BL 1T1R_W7_RRAM_W0p5_16_08_layout_0[15]/WL
+ 1T1R_W7_RRAM_W0p5_16_08_layout_0[9]/SL VSUBS x1T1R_W7_RRAM_W0p5_16_08_layout
.ends

VSS

is the only signal connected to the subcircuits.

.subckt x1T1R_16x16_W7_RRAM_W0p5_16_08_layout WL[0] WL[1] WL[2] WL[3] WL[4] WL[5]
+ WL[6] WL[7] WL[8] WL[9] WL[10] WL[11] WL[12] WL[13] WL[14] WL[15] BL[0] BL[1] BL[2]
+ BL[3] BL[4] BL[5] BL[6] BL[7] BL[8] BL[9] BL[10] BL[11] BL[12] BL[13] BL[14] BL[15]
+ SL[0] SL[1] SL[2] SL[3] SL[4] SL[5] SL[6] SL[7] SL[8] SL[9] SL[10] SL[11] SL[12]
+ SL[13] SL[14] SL[15] VSS
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[0] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[1] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[2] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[3] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[4] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[5] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[6] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[7] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[8] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[9] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[10] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[11] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[12] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[13] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[14] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
X1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[15] VSS x1T1R_1x16_W7_RRAM_W0p5_16_08_layout
.ends

@Mitch Bailey I am running with layout spice first only>. I avoided creating labels at N-1 level , but created labels at the top. Since the netgen will flatten, when should not be a problem right ?

Problem is not with netgen, but with magic extraction. I don't know if you can skip levels when using labels in magic. @Tim Edwards?

Hi @Mitch Bailey - added labels in N-1 , now PASSED. Thanks alot. But still same query with @Tim Edwards , if we can skip labelling at lower hierarchies. x1T1R_1x16_W7_RRAM_W0p5_16_08_layout1T1R 1x16 W7 RRAM W0p5 16 08 layout 0[0]/x1T1R W7 RRAM W0p5 16 08 layout1T1R_W7_RRAM_W0p5_16_08_layout_0[15]//sky130_fd_pr__nfet_g5v0d10v5_Y5YTSN_0/sky130_fd_pr__nfet_g5v0d10v5:0 vs. 1T1R_16x1_W7u_xschem_RRAM_DEVICE_1608rram column[0]/1T1R W7u xschem RRAM DEVICE 1608rram[0]/sky130_fd_pr__nfet_g5v0d10v5M1 w circuit1: 49 circuit2: 7 (delta=150%, cutoff=7%) Result: Circuits match uniquely. Property errors were found. The following cells had property errors: x1T1R_16x16_W7_RRAM_W0p5_16_08_layout Logging to file "comp.out" disabled LVS Done.