@Mitch Bailey, Hi Mitch, When I check the lvs of my circuit, I meet the net mismatch problem, The original cdl and gds file is generated by OpenRoad flow, when I do the LVS using magic and netgen, I meet some problems, how can I solve it? Thank you very much! Attach the original cdl file generated by OpenRoad, the extraction lvs_mag file, and the lvs check report:

I would suggest looking into why these instances in your cdl are unconnected.

Xoutput5 net5 _unconnected_0 _unconnected_1 _unconnected_2
+ _unconnected_3 clk0b sky130_fd_sc_hd__buf_16
Xoutput4 net4 _unconnected_4 _unconnected_5 _unconnected_6
+ _unconnected_7 clk0 sky130_fd_sc_hd__buf_16
Xinput3 rst_n _unconnected_8 _unconnected_9 _unconnected_10
+ _unconnected_11 net3 sky130_fd_sc_hd__clkbuf_4
Xinput2 control _unconnected_12 _unconnected_13 _unconnected_14
+ _unconnected_15 net2 sky130_fd_sc_hd__clkbuf_1
Xinput1 clk_in _unconnected_16 _unconnected_17 _unconnected_18
+ _unconnected_19 net1 sky130_fd_sc_hd__clkbuf_2
...
Xoutput6 net6 _unconnected_20 _unconnected_21 _unconnected_22
+ _unconnected_23 clk1 sky130_fd_sc_hd__buf_16
Xoutput7 net7 _unconnected_24 _unconnected_25 _unconnected_26
+ _unconnected_27 clk1b sky130_fd_sc_hd__buf_16
Xclkbuf_0_clk clk _unconnected_28 _unconnected_29 _unconnected_30
+ _unconnected_31 clknet_0_clk sky130_fd_sc_hd__clkbuf_4
Xclkbuf_1_0_0_clk clknet_0_clk _unconnected_32 _unconnected_33
+ _unconnected_34 _unconnected_35 clknet_1_0_0_clk sky130_fd_sc_hd__clkbuf_4
Xclkbuf_1_1_0_clk clknet_0_clk _unconnected_36 _unconnected_37
+ _unconnected_38 _unconnected_39 clknet_1_1_0_clk sky130_fd_sc_hd__clkbuf_4
Xrebuffer1 u_DCDC_DIGITAL_NOISE_INJECTION/LFSR2/Q\[5\] _unconnected_40
+ _unconnected_41 _unconnected_42 _unconnected_43 net8 sky130_fd_sc_hd__dlygate4sd1_1
Xrebuffer2 u_DCDC_DIGITAL_NOISE_INJECTION/Q_internal _unconnected_44
+ _unconnected_45 _unconnected_46 _unconnected_47 net9 sky130_fd_sc_hd__buf_2

They appear to be all the power supply connections.

OK, I see, let me check them, thank you!