Hi , LVS issue of one level up. I have the LVS passing for the subblocks , But although the devices are same. not sure what is going wrong. I made sure to have labels at every layout block level this time. Does the naming of the internal nets matter ? Do they have to be same ? Thanks @Mitch Bailey

I suggest using the same names for subckts in the layout and schematic as much as possible. Netgen will try to match circuits with the same name and flatten them if it can't. If the names of matching cells are different, netgen flattens them by default. (Although you could add

equate "-circuit1 layout_name" "-circuit2 schematic_name"

to the setup file.) From your report, you can see that the layout is missing some

SL[0]

connections. My guess is that it should be connected to

VLS_16x2_1808_layout_WIRE_EXT_1/OUT[1

because that net has only 1 nfet and 1 pfet connection (and there's nothing like that in the schematic).

Net: SL[0]                                 |Net: SL[0]                                 
  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 16  |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 17  
                                           |  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1   
                                           |                                           
Net: /VLS_16x2_1808_layout_WIRE_EXT_2//VLS |Net: WL_int[15]                            
  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 5   |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 5   
  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 5   |  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 5   
                                           |                                           
Net: VLS_16x2_1808_layout_WIRE_EXT_1/OUT[1 |Net: WL_int[14]                            
  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 1   |  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 5   
  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 1   |  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 5

Also looks like

VDD_LOW

is shorted

Net: VDD_LOW                               |Net: VDD_LOW                               
  sky130_fd_pr__pfet_01v8/(1|3) = 96       |  sky130_fd_pr__pfet_01v8/(1|3) = 96       
  sky130_fd_pr__pfet_01v8/4 = 96           |  sky130_fd_pr__pfet_01v8/4 = 96           
  sky130_fd_pr__pfet_g5v0d10v5/(1|3) = 15  |                                           
  sky130_fd_pr__nfet_g5v0d10v5/(1|3) = 15  |

I'm guessing 3 of the

/VLS_16x2_1808_layout_WIRE_EXT_2//VLS

nets. Your long instance names are being truncated, which can cause difficulties when debugging.

export NETGEN_COLUMNS=80

before running netgen for wider reports. Internal nets do not have to have the same name.

Thanks let me check

You have 3 more nets in the schematic than in your layout. Probably due to the

VDD_LOW

shorts.