Hello there, I have two questions about fanout counts. 1) I checked some of the fanout violated pins in the output verilog file and I realized that when I set SYNTH_MAX_FANOUT to 5, the pin was used as input in 5 logic gates and 5 Antenna diodes. Therefore, the tool warns this pin with 10 fanout. My question is that do antenna diodes contributes to fanout count of a pin? 2) In this issue comment "https://github.com/The-OpenROAD-Project/OpenLane/issues/1206#issuecomment-1188363224", antonblanchard says "Fan out violations in clock tree synthesis and antenna fix up pays no attention to max fan out constraints.". So, the real fanout count should not consider the gates added in the cts and antenna fix up, right? Thanks

I keep saying this - I don't think it makes any sense to check max fanout at the end of the flow. Max cap & slew are more meaningful at that point. I feel this is a flow bug. That's just my opinion though

Thanks for your answer