I m having some trouble with running the default `user proje open-source-silicon.dev #openlane

I'm having some trouble with running the default `...

Keoni Gandall

07/30/2022, 3:28 PM

I'm having some trouble with running the default

user_project

provided by https://github.com/efabless/caravel_user_project, and I think the problem may be during checking with openlane. On a fresh pull, I am getting "max fanout violations". Perhaps this is due to "This PDK does not support cvc" (I don't know what cvc means, and googling it is difficult. I included full logs with https://github.com/efabless/caravel_user_project/issues/150 (this is from stdout, stderr has no errors). Any thoughts? Thanks

Mitch Bailey

07/30/2022, 4:28 PM

There are 2 CVC programs. One is OSS CVC Verilog and the other is an ERC like program that I eventually plan to rename CVC-RV (for reliability verification). It will not cause your flow to fail.

Arman Avetisyan

07/30/2022, 5:06 PM

"I'm having some trouble with running the default

user_project"

you provided warning only. What is the reason why you concluded that the flow is failing?

Keoni Gandall

07/30/2022, 5:49 PM

Ok, so the cvc doesn't matter right? Or will be replaced later.

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There are max fanout violations in the design at the typical corner

I assume that max fanout violations are a bad thing that ought to be fixed

Arman Avetisyan

07/30/2022, 5:52 PM

Yeah, there is a bug that diodes count as "fanouts" but should not

Arman Avetisyan

07/30/2022, 5:52 PM

My point is: Its a warning. The flow should pass without failures

Keoni Gandall

07/30/2022, 6:15 PM

Oh wonderful. Good to know

Keoni Gandall

07/31/2022, 2:23 PM

@Arman Avetisyan Timothy Edwards responded on github to your "bug that diodes count as fanouts" with - "A diode is a connection with a capacitive load. Why should it not count as part of the fanout? Of course it's part of the fanout." Is there a particular distinction that makes this important?

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