Hi, I only changed FP_PDN_MACRO_HOOKS variable from "open_ram_2k vccd1 vssd1" to "open_ram_2k vccd1 vssd1 vccd1 vssd1" to overcome the issue in PDN stage in config.tcl file. My design in mpw6 tag run successfully but with the same verilog codes and config.tcl (only FP_PDN_MACRO_HOOKS changed) I got error in DETAILED ROUTING: Net instr_mem.sp_ram_wrap_i.vccd1 of signal type SIGNAL cannot be connected to iterm instr_mem.sp_ram_wrap_i.open_ram_2k/vccd1 with signal type POWER Couldn't solve the issue myself. Is there anyone used macro with new MACRO_HOOKS change and complete the flow? What should be the proper config.tcl with macros such as OpenRAM

Do you have the vccd1 defines a pin in your verilog? Typically you have the verilog but with two variants depending on definition of POWER_PINS macro. This macro's name is defined in config.tcl

is the flow generated any

issue_reproducible

inside

runs

directory?

set ::env(VDD_NETS) [list {vccd1}] set ::env(GND_NETS) [list {vssd1}] this is the config.tcl related to this I think and this is the openram instantiation verilog: sky130_sram_2kbyte_1rw1r_32x512_8 open_ram_2k( `ifdef USE_POWER_PINS .vccd1(vccd1), .vssd1(vssd1), `endif .clk0(clk), .csb0(1'b0), .web0(~(we_i & ~bypass_en_i)), .wmask0(be_i), .addr0(addr_i[10:2]), .din0(wdata_i), .dout0(ram_out_int), .clk1(1'b0), .csb1(1'b1), .addr1(9'b000000000), .dout1() );

Do you have SYNTH_USE_PG_PINS_DEFINES set?

set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"

please post the top module's pins declaration

`define USE_POWER_PINS module core_region #( parameter AXI_ADDR_WIDTH = 32, parameter AXI_DATA_WIDTH = 64, parameter AXI_ID_MASTER_WIDTH = 10, parameter AXI_ID_SLAVE_WIDTH = 10, parameter AXI_USER_WIDTH = 0, // parameter DATA_RAM_SIZE = 32768, // in bytes // parameter INSTR_RAM_SIZE = 32768, // in bytes parameter DATA_RAM_SIZE = 2048, // in bytes parameter INSTR_RAM_SIZE = 2048, // in bytes parameter USE_ZERO_RISCY = 1, parameter RISCY_RV32F = 0, parameter ZERO_RV32M = 1, parameter ZERO_RV32E = 0 ) ( `ifdef USE_POWER_PINS vccd1, // User area 1 1.8V supply vssd1, // User area 1 digital ground `endif clk, rst_n, testmode_i, fetch_enable_i, irq_i, core_busy_o, clock_gating_i, boot_addr_i, core_master_aw_addr, core_master_aw_prot, core_master_aw_region, core_master_aw_len, core_master_aw_size, core_master_aw_burst, core_master_aw_lock, core_master_aw_cache, core_master_aw_qos, core_master_aw_id, core_master_aw_user, core_master_aw_ready, core_master_aw_valid, core_master_ar_addr, core_master_ar_prot, core_master_ar_region, core_master_ar_len, core_master_ar_size, core_master_ar_burst, core_master_ar_lock, core_master_ar_cache, core_master_ar_qos, core_master_ar_id, core_master_ar_user, core_master_ar_ready, core_master_ar_valid, core_master_w_valid, core_master_w_data, core_master_w_strb, core_master_w_user, core_master_w_last, core_master_w_ready, core_master_r_data, core_master_r_resp, core_master_r_last, core_master_r_id, core_master_r_user, core_master_r_ready, core_master_r_valid, core_master_b_resp, core_master_b_id, core_master_b_user, core_master_b_ready, core_master_b_valid, dbg_master_aw_addr, dbg_master_aw_prot, dbg_master_aw_region, dbg_master_aw_len, dbg_master_aw_size, dbg_master_aw_burst, dbg_master_aw_lock, dbg_master_aw_cache, dbg_master_aw_qos, dbg_master_aw_id, dbg_master_aw_user, dbg_master_aw_ready, dbg_master_aw_valid, dbg_master_ar_addr, dbg_master_ar_prot, dbg_master_ar_region, dbg_master_ar_len, dbg_master_ar_size, dbg_master_ar_burst, dbg_master_ar_lock, dbg_master_ar_cache, dbg_master_ar_qos, dbg_master_ar_id, dbg_master_ar_user, dbg_master_ar_ready, dbg_master_ar_valid, dbg_master_w_valid, dbg_master_w_data, dbg_master_w_strb, dbg_master_w_user, dbg_master_w_last, dbg_master_w_ready, dbg_master_r_data, dbg_master_r_resp, dbg_master_r_last, dbg_master_r_id, dbg_master_r_user, dbg_master_r_ready, dbg_master_r_valid, dbg_master_b_resp, dbg_master_b_id, dbg_master_b_user, dbg_master_b_ready, dbg_master_b_valid, data_slave_aw_addr, data_slave_aw_prot, data_slave_aw_region, data_slave_aw_len, data_slave_aw_size, data_slave_aw_burst, data_slave_aw_lock, data_slave_aw_cache, data_slave_aw_qos, data_slave_aw_id, data_slave_aw_user, data_slave_aw_ready, data_slave_aw_valid, data_slave_ar_addr, data_slave_ar_prot, data_slave_ar_region, data_slave_ar_len, data_slave_ar_size, data_slave_ar_burst, data_slave_ar_lock, data_slave_ar_cache, data_slave_ar_qos, data_slave_ar_id, data_slave_ar_user, data_slave_ar_ready, data_slave_ar_valid, data_slave_w_valid, data_slave_w_data, data_slave_w_strb, data_slave_w_user, data_slave_w_last, data_slave_w_ready, data_slave_r_data, data_slave_r_resp, data_slave_r_last, data_slave_r_id, data_slave_r_user, data_slave_r_ready, data_slave_r_valid, data_slave_b_resp, data_slave_b_id, data_slave_b_user, data_slave_b_ready, data_slave_b_valid, instr_slave_aw_addr, instr_slave_aw_prot, instr_slave_aw_region, instr_slave_aw_len, instr_slave_aw_size, instr_slave_aw_burst, instr_slave_aw_lock, instr_slave_aw_cache, instr_slave_aw_qos, instr_slave_aw_id, instr_slave_aw_user, instr_slave_aw_ready, instr_slave_aw_valid, instr_slave_ar_addr, instr_slave_ar_prot, instr_slave_ar_region, instr_slave_ar_len, instr_slave_ar_size, instr_slave_ar_burst, instr_slave_ar_lock, instr_slave_ar_cache, instr_slave_ar_qos, instr_slave_ar_id, instr_slave_ar_user, instr_slave_ar_ready, instr_slave_ar_valid, instr_slave_w_valid, instr_slave_w_data, instr_slave_w_strb, instr_slave_w_user, instr_slave_w_last, instr_slave_w_ready, instr_slave_r_data, instr_slave_r_resp, instr_slave_r_last, instr_slave_r_id, instr_slave_r_user, instr_slave_r_ready, instr_slave_r_valid, instr_slave_b_resp, instr_slave_b_id, instr_slave_b_user, instr_slave_b_ready, instr_slave_b_valid, debug_req, debug_gnt, debug_rvalid, debug_addr, debug_we, debug_wdata, debug_rdata, tck_i, trstn_i, tms_i, tdi_i, tdo_o ); //parameter AXI_ADDR_WIDTH = 32; //parameter AXI_DATA_WIDTH = 64; //parameter AXI_ID_MASTER_WIDTH = 10; //parameter AXI_ID_SLAVE_WIDTH = 10; //parameter AXI_USER_WIDTH = 0; parameter AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8; parameter ADDR_WIDTH = AXI_ADDR_WIDTH; //parameter DATA_RAM_SIZE = 2048; //parameter INSTR_RAM_SIZE = 2048; //parameter USE_ZERO_RISCY = 1; //parameter RISCY_RV32F = 0; //parameter ZERO_RV32M = 1; //parameter ZERO_RV32E = 0; parameter AXI_ID_WIDTH = AXI_ID_MASTER_WIDTH; inout wire vccd1; inout wire vssd1;

The "inout wire vccd1; inout wire vssd1;" should be enclosed in `ifdef `endif

is it with new openlane, i got no issue about it in mpw6

Can you try my suggestion?

ok now I will try immediately thanks

@Burak Aykenar you've used wrong instance name for power hooks.

himmm, should it be like: set ::env(FP_PDN_MACRO_HOOKS) "\ data_mem.open_ram_2k vccd1 vssd1 vccd1 vssd1,\ instr_mem.sp_ram_wrap_i.open_ram_2k vccd1 vssd1 vccd1 vssd1"

yes

Use the names from synthesis verilog

I rerun and got no error in DRT stage for now, it is still running, thanks a lot btw, do you see any hope in this DTR run to be finished before the judgement day 🙂 [INFO DRT-0195] Start 9th optimization iteration. Completing 10% with 12471 violations. elapsed time = 000000, memory = 12804.62 (MB). Completing 20% with 12471 violations. elapsed time = 000000, memory = 12804.62 (MB). Completing 30% with 12442 violations. elapsed time = 000449, memory = 12793.84 (MB). Completing 40% with 12442 violations. elapsed time = 000449, memory = 12793.84 (MB). Completing 50% with 12442 violations. elapsed time = 000449, memory = 12793.84 (MB). Completing 60% with 12188 violations. elapsed time = 001118, memory = 12723.07 (MB). Completing 70% with 12188 violations. elapsed time = 001118, memory = 12723.07 (MB). Completing 80% with 12174 violations. elapsed time = 001716, memory = 12705.36 (MB). Completing 90% with 12174 violations. elapsed time = 001716, memory = 12705.36 (MB). Completing 100% with 12174 violations. elapsed time = 002527, memory = 12509.18 (MB). [INFO DRT-0199] Number of violations = 12174. [INFO DRT-0267] cpu time = 003359, elapsed time = 002528, memory = 12509.21 (MB), peak = 13884.42 (MB) Total wire length = 3863418 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 1607874 um. Total wire length on LAYER met2 = 1983046 um. Total wire length on LAYER met3 = 173288 um. Total wire length on LAYER met4 = 99209 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 298164. Up-via summary (total 298164):. ------------------------- FR_MASTERSLICE 0 li1 114686 met1 157749 met2 19120 met3 6609 met4 0 ------------------------- 298164 [INFO DRT-0195] Start 10th optimization iteration. Completing 10% with 12174 violations. elapsed time = 000000, memory = 12509.21 (MB). Completing 20% with 12174 violations. elapsed time = 000000, memory = 12509.21 (MB). Completing 30% with 11724 violations. elapsed time = 000653, memory = 12544.56 (MB). Completing 40% with 11724 violations. elapsed time = 000653, memory = 12544.56 (MB). Completing 50% with 11724 violations. elapsed time = 002422, memory = 11293.98 (MB). Completing 60% with 11724 violations. elapsed time = 002422, memory = 11294.13 (MB). Completing 70% with 11724 violations. elapsed time = 002422, memory = 11294.20 (MB). Completing 80% with 11355 violations. elapsed time = 003100, memory = 11328.68 (MB). Completing 90% with 11355 violations. elapsed time = 003100, memory = 11328.68 (MB). Completing 100% with 10957 violations. elapsed time = 004003, memory = 11391.44 (MB). [INFO DRT-0199] Number of violations = 10957. [INFO DRT-0267] cpu time = 004549, elapsed time = 004003, memory = 11394.51 (MB), peak = 13884.42 (MB) Total wire length = 3864779 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 1605992 um. Total wire length on LAYER met2 = 1982000 um. Total wire length on LAYER met3 = 174713 um. Total wire length on LAYER met4 = 102074 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 299077. Up-via summary (total 299077):. ------------------------- FR_MASTERSLICE 0 li1 114686 met1 158276 met2 19249 met3 6866 met4 0 ------------------------- 299077 [INFO DRT-0195] Start 11th optimization iteration. Completing 10% with 10957 violations. elapsed time = 000000, memory = 11394.53 (MB). Completing 20% with 10957 violations. elapsed time = 000000, memory = 11394.53 (MB). Completing 30% with 10149 violations. elapsed time = 002014, memory = 11396.13 (MB). Completing 40% with 10149 violations. elapsed time = 002014, memory = 11396.77 (MB). Completing 50% with 10149 violations. elapsed time = 002153, memory = 11399.57 (MB). Completing 60% with 9931 violations. elapsed time = 002153, memory = 11399.57 (MB). Completing 70% with 9931 violations. elapsed time = 002153, memory = 11399.67 (MB). Completing 80% with 9897 violations. elapsed time = 004003, memory = 11371.09 (MB). Completing 90% with 9897 violations. elapsed time = 004003, memory = 11371.09 (MB). Completing 100% with 9895 violations. elapsed time = 004813, memory = 11425.95 (MB). [INFO DRT-0199] Number of violations = 9895. [INFO DRT-0267] cpu time = 005134, elapsed time = 004813, memory = 11426.16 (MB), peak = 13884.42 (MB) Total wire length = 3865203 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 1605363 um. Total wire length on LAYER met2 = 1980601 um. Total wire length on LAYER met3 = 175126 um. Total wire length on LAYER met4 = 104111 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 299464. Up-via summary (total 299464):. ------------------------- FR_MASTERSLICE 0 li1 114686 met1 158534 met2 19317 met3 6927 met4 0 ------------------------- 299464 [INFO DRT-0195] Start 12th optimization iteration. Completing 10% with 9895 violations. elapsed time = 000000, memory = 11426.16 (MB). Completing 20% with 9895 violations. elapsed time = 000000, memory = 11426.36 (MB). Completing 30% with 9539 violations. elapsed time = 001809, memory = 11393.78 (MB). Completing 40% with 9539 violations. elapsed time = 001809, memory = 11393.87 (MB). Completing 50% with 9539 violations. elapsed time = 001938, memory = 11430.66 (MB). Completing 60% with 9533 violations. elapsed time = 001939, memory = 11430.67 (MB). Completing 70% with 9533 violations. elapsed time = 001939, memory = 11430.79 (MB). Completing 80% with 9516 violations. elapsed time = 003548, memory = 11407.32 (MB). Completing 90% with 9516 violations. elapsed time = 003548, memory = 11407.32 (MB). I increased swap area otherwise it kills the process, what could cause these long runs and what can improve run latency, more powerful CPU or more RAM, I will run this in our server but its CPU is not that better but has 32 GB instead of 16 GB, any idea ?

hard to say

are you running single cpu?

yes I am trying to make area smaller and try new flows. I have ROUTING_CORES 8 in config file, is there any other multithreading option in config file?

Were you setting absolute size the whole time?

@Matt Venn yes, I somehow thought that it is the best way to achieve min area, isn't it?

I would start by giving the defaults for density and letting the floorplanner choose it's own size. That would be my starting point to optimise from.