what is a reasonable clock rate for a SHA256 or si...
# sky130
a
what is a reasonable clock rate for a SHA256 or similar circuit in the SKY130 process?
t
There is a huge design space depending on the architecture you pick ... and then the area you want to use and the power ...
But you're not going to make a competitive crypto hasher in sky130 for sure ...
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a
this is not for a crypto miner project but something somewhat related, but def. not competing with miners because I'd have to use the best 3nm tech for that...
what would be the best design to maximize the throughput for a 15 mm2 area (so fastest for smallest area given the use of many cores in parallel)? Any advice would be greatly appreciated!
t
Probably use the
_hs
cells, then a fully pipelined implementation, make the pipelining stage configurable and then check the STA to balance area vs speed and see where you can get the best ratio. Then put as many of the resulting core as you can in your area. Depending on what you need to hash, the IO speed might be a limit ...
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a
STA? What does that stand for?
would you know anyone for hire who could help with such a design? I am an analog designer and a programmer but not a Verilog designer although I know a few things about it but not enough...
t
STA is "Static Timing Analysis". Basically you need to implement it, look at the result, and iterate.
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a
Alex, Please put the request out on the announcement or general channel. There are a lot of people able to do work who are active on the channels. Also @jeffdi This is not the first request for services. We need to enable this more. On subject matter, the width of your multipleier matters but single cycle 32 bit multiply is comfortably possible at >100Mhz on this tech with HS library. With optimization of the chozen mutliply implementation I'm sure you could do a lot better. Also it matters the environment you need the silicon to work in. Will it be hot or room temperature. What power supply will be applied? (How well will power be regulated) (Die voltage and temp have very significant 1st order effect on cmos gate speeds.) Running cooler and slightly higher voltage can buy a lot of performance improvements. (Ask anybody who ever built an overclocked gaming PC.)
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a
the good thing is I can control temp and supply voltage as I want since this is for my own project.
l
FWIW, I worked on this SHA-256 core last year, and there's some data in the paper that you may find useful — check Figures 9, 10, and 11. We managed to achieve over 100MHz using a simple implementation (no pipeline) and
sky130_fd_sc_hd
cells. Both the speed and power consumption data were taken from OpenROAD.
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a
Thank you so much Lucas!