So what you're seeing is diff/tap and psdm (the left side is in a nwell, hidden layer). Is that valid ? It passed

mpw_precheck

... but still the 0.11u between the

psdm

and the

ndiff

on the left is less than 0.13u from

psd.7

. Or is it ok because there is an abutting edge ?

@tnt Interesting… magic drc uses magic layers, some of which are calculated, and may not correspond to the layers actually read in. @Tim Edwards is this correct? I’ve gds with implant layers in one large rectangle over the diffusion, but magic reporting width error because abutting cells have offset diffusion. Maybe drc on gds in magic should be done with

gds maskhints yes

? In klayout, drc may be running in deep mode where this would pass, but be caught in flat mode.

@Mitch Bailey I should maybe have said that here I drew the middle part manually with the MASK_HINTS. By default magic would create one that has a part narrower than 0.38 and this would fail precheck. So I extended the middle part to be 0.38 manually. (Note that even in the one auto drawn by magic, it would still be closer than 0.13u, it was 0.125u from the opposite diffusion).

I think it's an error. Magic's DRC sometimes doesn't anticipate the effect of mask hints, and is probably implementing the rule according to the distance between diffusion and tap, not the distance between diffusion and implant. I see on only

psd.1

and

psd.2

in the MR deck rules; generally, implant layer width and spacing are the two critical measurements that form an actual manufacturing rule violation (i.e., could physically screw up the mask by creating tiny areas of material that flake away and drift around). Situations like this underscore the need for a full DRC deck for klayout. Implementing just the MR rules in klayout is insufficient, and implementing a full deck in magic just slows it down, although it can be done in a drc style that is intended to be run in batch mode.

@Tim Edwards I fixed the issue for future submissions, but is there anything we must do for CI2406 ?

For a difference between 0.13um and 0.11um, you might see some small difference in transistor behavior, but I doubt it.

@Tim Edwards Ok, just wanted to make sure it wasn't going to be an issue if skywater noticed the violation or something and get the design thrown out 😅

They will only reject based on manufacturing rule violations. This error won't cause a rejection.