So in xschem I shorted some ports together with 0R resistors. Unfortunately AFAICT that doesn't really work, netgen seems to only consider the "Layout" side 0R resistors as shorts, so the design fails pin matching. Because says I have pin1 / pin2 and pin3 shorted. In xschem spice, I might end up with :

R1 pin1 pin2 0
R2 pin1 pin3 0

But then in the extracted spice which signal gets "picked" as the reference one might be different :

R1 pin2 pin1 0
R1 pin3 pin1 0

And LVS won't match ...

@tnt Are you using a relatively new version of netgen? This works in digital designs where verilog assigns the same net to several ports (which become effectively shorted). In xschem with analog designs, I’ve seen

generic_m*

resistors implemented to prevent shorts in extraction/netlisting. @Tim Edwards any advice?

Yeah, I know this works with digital designs where the "Schematic" side is verilog. But here because it's an analog design, I have two spice has input.

I have two spice has input.

Not sure what you mean. Do you have 2 external inputs that need to connect to the same circuit input?

No I mean in LVS I'm not comparing a verilog file with an extracted SPICE file. I'm comparing the SPICE netlist produced by xschem with the SPICE netlist produced from magic extraction.

@tnt: Yes, I'm aware that the extraction of resistor shorts is arbitrary and can result in a netlist mismatch. The only way to work around it is to insert metal resistors into both the layout and schematic, rather than relying on automatic insertion of resistor shorts.

That's what I did so far just to "check" was to manually modify the "schematic" spice to match the extracted one just to see LVS pass (obviously making sure I only change the 0R resistors 😅 ). I've been trying to read the netgen source code, but I have no idea how it does what it does 😅

@tnt

I’ve been trying to read the netgen source code, but I have no idea how it does what it does

I feel your pain.😬

I fully endorse the usage of 'metal resistors' to implement shorts, metal options and whatsoever. Any other solution sooner or later will come back badly as a boomerang breaking things somewhere down the flow. Usually a metal resistor is just a small section of the metal interconnection surrounded by some 'Resistor ID layer' (so netgen recognizes this as a resistor to match with the schematic). This allows to match the metal resistor in the schematic (a 0 Ohm resistor) with the metal resistor on the layout. Keep in mind that you are not adding any real resistor to your design, it's just a trick to allow node aliases and reliable LVS matching.

Heh, still looks like a hack to me ... and your "metal resistor" layout still need to match between schematic and layout. If you have port A / B / C shorted and you put a resistor between A-B and then A-C, you also need that in your layout and not A-B and then B-C because it was more convenient during layout to have metal like that for instance. I can understand than in the extracted spice netlist, zero resistors are needed simply because spice can't have multiple name for a net and you have a 1:1 mapping between port and net in subcircuits. But if you load your "reference" schematic from verilog, then you can have multiple nets wired together just fine and

netgen

will also match it properly to zero-ohm shorts in the extracted layout, so it must already have some ability to represent multiple names for the same node internally somehow (since it does it fine for verilog), so it would be nice if there was a way to represent that in the "schematic" side spice file too, either through zero-ohm resistors, or some other special "short" notation or something.