I found something strange that need fixing , if some node specially VSS ,VDD. If it connected with say chunk of 6 transistor at one place and say 4 at one place but both these chunks are not joined to make common VDD VSS in layout it won’t raise lvs error also simulation runs perfectly. @Mitch Bailey @Tim Edwards it is logical because in spice both these chunk with VSS is VSS in magic spice so simulation will run but actually hardware will have issue. It happens to me not once but twice.

@Atif Khan Are you referring to soft connections? I mean connections through nwell or psubstrate. You are correct in that magic does not detect connections through nwell or psubstrate as an error. However, there is a soft connection check in precheck.

Yes exactly i am referring to vdd and vss connection that are connected to nwell/psub that are separated and not connected either by any metal or well.

precheck’s soft connection should fail if there are those types of errors. @Atif Khan thanks for mentioning this. It’s important that designers understand this issue.

Thanks